Software programmable verification tool having multiple built-in self-test (BIST) modules for testing and debugging multiple devices under test (DUT)

A system for testing and debugging an embedded device under test, the system comprising:

• at least one loader adapted to load an instruction into a parameterized shift register of each of a plurality of BIST modules, said each of said plurality of BIST modules coupled to an individual one of a plurality of embedded memory modules comprising the embedded device under test;
• at least one identifier adapted to determine an identity of each of said instruction loaded into said parameterized shift register of said each of said plurality of BIST modules;
• and
• at least one generator adapted to generate a separate test signal from said each of said plurality of BIST modules corresponding to said determined identity of said instruction loaded in said each of said plurality of BIST modules, said each one of said generated test signals causing control and execution of the testing and debugging of a corresponding one of each of said plurality of embedded memory modules comprising the embedded device under test.

A machine-readable storage, having stored thereon a computer program having at least one code section for testing and debugging an embedded device under test, the code sections executable by a machine for causing the machine to perform the steps comprising:

• loading an instruction into a parameterized shift register of each one of a plurality of BIST modules coupled to an individual one of a plurality of embedded memory modules comprising the embedded device under test;
• determining an identity of each of said instruction loaded into said parameterized shift register of said each of said plurality of BIST modules;
• and
• generating a separate test signal from said each of said plurality of BIST modules corresponding to said determined identity of said instruction loaded in s said each of said plurality of BIST modules, said each one of said generated test signals causing control and execution of the testing and debugging of a corresponding one of each of said plurality of embedded memory modules comprising the embedded device under test.