Data flow oriented storage

A data processing system, comprising:

• a central processing unit (CPU);
• random access memory (RAM);
• read only memory (ROM);
• an I/O adapter;
• and
• a bus system coupling devices internal to said CPU, said CPU comprising an apparatus for managing operations within a processor of said CPU, said apparatus comprising:
• a plurality of addressable registers, each of said addressable registers partitioned into plurality of data entry fields;
• a first comparison circuit, said first comparison circuit operable to scan and compare a predetermined input value to a value from a first data entry field selected from each of said addressable registers;
• a second comparison circuit, said second comparison circuit operable to compare a first register address corresponding to a comparison match of said first comparison circuit to a second register address;
• and
• a dispatch circuit operable to dispatch data in a second data entry field of a second register to an operation unit, said second register corresponding to said second register address in response to a decode of data in a third data entry field of said second register and a comparison match of said second comparison circuit.

A method for a Load operation in a Load and Store operation unit comprising the steps of:

• issuing concurrently a fetch instruction requesting a real address to a data cache and a Storage Reference Buffer (SRB), said real address corresponding to an address of multiple bytes of data;
• checking said SRB for said real address;
• receiving said multiple bytes of data from said SRB if said real address is available;
• retrieving said multiple bytes of data first from said SRB if said real address is available and second from said data cache if said real address is not available in said SRB;
• and
• updating a corresponding SRB register with said multiple bytes of data.

A method for a Store operation in a Load and Store operation unit comprising the steps of:

• issuing a real address generation instruction;
• looking up said real address in a table lookup buffer;
• sending said real address to a miss resolution processor if said real address is not in said table lookup buffer, said miss resolution processor determining a translated real address;
• sending said real address from one of said miss resolution processor and said table lookup buffer to a Storage Reference Buffer (SRB);
• and
• updating corresponding data entry fields in said SRB.

A method for a Store operation in a Load and Store operation unit comprising the steps of:

• issuing an address generation instruction by a first instruction unit, said address generation instruction generating a real address in memory;
• updating said real address in a real address field of a register in a Storage Reference Buffer;
• sending concurrently, a request for a multiple byte word with said real address to said Storage Reference Buffer and a data cache;
• receiving said multiple byte word from one of said Storage Reference Buffer and said data cache;
• updating said multiple byte word from said data cache with an operand mask;
• receiving from said first instruction unit store data operand;
• aligning said store data operand to said multiple bytes of data;
• and
• updating said multiple bytes of data with said operand mask complement.

A method for a Load operation in a Load and Store operation unit comprising the steps of:

• issuing an address generation instruction by a first instruction unit, said address generation instruction generating a real address in memory;
• updating said real address in a real address field of a register in a Storage Reference Buffer;
• sending concurrently, a request for a multiple byte word with said real address to said Storage Reference Buffer and a data cache;
• receiving said multiple byte word from one of said Storage Reference Buffer and said data cache;
• extracting selected bytes from said multiple byte word;
• receiving said selected bytes by said first instruction unit;
• and
• updating said multiple bytes of data with said operand mask complement.