Method, apparatus and system for acquiring a global promotion facitily utilizing a data-less transaction

A processor for a data processing system having a global promotion facility and a plurality of processors coupled by an interconnect, said processor comprising:

• an instruction sequencing unit;
• an execution unit that executes an acquisition instruction;
• means for transmitting an address-only operation on the interconnect to acquire a promotion bit field within the global promotion facility while excluding at least one other processor among the plurality of processors;
• and
• means, responsive to receipt of a combined response for said address-only operation representing a collective response of others of said plurality of processors to said address-only operation, for determining whether or not acquisition of said promotion bit field was successful by reference to said combined response.

A data processing system, comprising:

• a global promotion facility containing a promotion bit field;
• and
• a plurality of processors coupled to said global promotion facility and to an interconnect, wherein said plurality of processors includes a second processor and a first processor, said first processor comprising:
• an instruction sequencing unit;
• an execution unit that executes an acquisition instruction;
• means for transmitting an address-only operation on the interconnect to acquire a promotion bit field within the global promotion facility while excluding at least the second processor;
• and
• means, responsive to receipt of a combined response for said address-only operation representing a collective response of others of said plurality of processors to said address-only operation, for determining whether or not acquisition of said promotion bit field was successful by reference to the combined response.