US 2004/0073623 A1 · Pipelining cache-coherence operations in a shared-memory multiprocessing system

Abstract

One embodiment of the present invention provides a system that facilitates pipelining cache coherence operations in a shared memory multiprocessor system. During operation, the system receives a command to perform a memory operation from a processor in the shared memory multiprocessor system. This command is received at a bridge that is coupled to the local caches of the processors in the shared memory multiprocessor system. If the command is directed to a cache line that is subject to an in-progress pipelined cache coherency operation, the system delays the command until the in-progress pipelined cache coherency operation completes. Otherwise, the system reflects the command to local caches of other processors in the shared memory multiprocessor system. The system then accumulates snoop responses from the local caches of the other processor and sends the accumulated snoop response to the local caches of other processors in the shared memory multiprocessor system.

Claims22

Dependent claims

A method for pipelining cache coherence operations in a shared memory multiprocessor system, comprising:

receiving a command to perform a memory operation from a processor in the shared memory multiprocessor system;
wherein the command is received at a coherence circuit that is coupled to local caches of processors in the shared memory multiprocessor system;
and
if the command is directed to a cache line that is subject to an in-progress pipelined cache coherency operation, delaying the command until the in-progress pipelined cache coherency operation completes.

1 more element

Dependencies are inferred from the claim text.

Pipelining cache-coherence operations in a shared-memory multiprocessing system

Life of this patent

Pipelining cache-coherence operations in a shared-memory multiprocessing system

Life of this patent

Abstract

Claims22