Non-oxidizing spacer densification method for manufacturing semiconductor devices

A method of forming a semiconductor structure on a substrate, comprising:

• forming a polycide structure comprising at least one polysilicon layer and at least one metal suicide layer;
• forming a spacer oxide on said polycide structure, said spacer oxide being formed to at least partially surround said polycide structure;
• and
• densifying said spacer oxide in a non-oxidizing ambient to form said semiconductor structure.

A method of forming a non-volatile memory stack structure and a non-memory control gate stack structure of an integrated semiconductor device on a silicon substrate, said method comprising:

• forming a dielectric isolation region on said silicon substrate, said dielectric isolation region being formed between an active non-volatile memory mesa area and an active non-memory mesa area of said silicon substrate;
• forming a memory cell oxide layer on said silicon substrate over said active nonvolatile memory mesa area;
• forming a doped floating gate polysilicon layer on said memory cell oxide layer over said active non-volatile memory mesa area;
• forming an inter-poly oxide layer on said doped floating gate polysilicon layer over said active non-volatile memory mesa area;
• forming a thin gate oxide layer on said silicon substrate over said active non-memory mesa area;
• forming a doped control gate polysilicon layer on said thin gate oxide of said active non-memory mesa area and on said inter-poly oxide layer of said active nonvolatile memory mesa area;
• forming a refractory metal silicide layer on said doped control gate polysilicon layer over said active non-volatile memory mesa area so as to form a non-volatile memory stack structure over said active non-volatile memory mesa area;
• forming heavily doped non-volatile memory source/drain regions of said nonvolatile memory stack structure in said silicon substrate over said active non-volatile memory mesa area;
• forming a refractory metal silicide layer on said doped control gate polysilicon layer over said active non-memory mesa area so as to form a non-memory control gate stack structure over said active non-memory mesa area;
• forming lightly doped non-memory source/drain regions of said non-memory control gate stack structure in said silicon substrate over said active non-memory mesa area;
• forming a spacer oxide side layer on each of said non-volatile memory stack and said non-memory control gate stack structures;
• densifying said spacer oxide side layers in a non-oxidizing ambient;
• and
• forming heavily doped non-memory source/drain regions of said non-memory control gate stack structure in said silicon substrate over said lightly doped non-memory source/drain regions.