DSP unit for multi-level global accumulation

A system comprising:

• an SRAM-memory device;
• a clock;
• and
• a digital signal processor coupled to the memory device and the clock, the digital signal-processor including
• a first stage having a plurality of absolute difference-determinators to calculate the absolute difference of a plurality of data sets;
• a second stage to combine the absolute differences of the plurality of data sets into at least two intermediate values for two different sum of absolute differences calculations wherein the second stage is provided by reconfiguring a multiplier;
• and
• a third stage including at least two accumulators to accumulate each of the intermediate values to determine two sum of absolute differences values from the plurality of data sets in parallel.