Enhanced protection for input buffers of low-voltage flash memories

An input buffer for a low-voltage flash memory device, comprising:

• an input stage having a transistor that includes a gate, a drain, and a source, wherein the gate is receptive to an inhibiting signal, wherein the drain is receptive to an input signal, wherein the transistor inhibits the input signal from being presented at the source when the inhibiting signal is at a first predetermined level;
• an output stage having an inverter that includes a first connection and a second connection, wherein the first connection is coupled to the source of the transistor, and wherein the second connection presents the input signal to the low-voltage flash memory device;
• and
• a voltage sensor to trigger when the input signal is at a second predetermined level, wherein the voltage sensor is receptive to a pumped signal and the input signal.

An input buffer for a low-voltage flash memory device, comprising:

• an input stage having a transistor that includes a gate, a drain, and a source, wherein the gate is receptive to an inhibiting signal, wherein the drain is receptive to an input signal, wherein the transistor inhibits the input signal from being presented at the source when the inhibiting signal is at a first predetermined level;
• an output stage having an inverter that includes a first connection and a second connection, wherein the first connection is coupled to the source of the transistor, and wherein the second connection presents the input signal to the low-voltage flash memory device;
• and
• an inhibiting circuit to selectively produce the inhibiting signal, wherein the inhibiting circuit is receptive to a pumped signal and a sensed signal.

An input buffer for a low-voltage flash memory device, comprising:

• an input stage having a first n-channel transistor that includes a gate, a drain, and a source, wherein the gate is receptive to an inhibiting signal, wherein the drain is receptive to an input signal, wherein the input stage inhibits the input signal from being presented at the source when the inhibiting signal is at a low level;
• an output stage to present the input signal to the low-voltage flash memory device, wherein the output stage includes:
• a second n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the first n-channel transistor, wherein the source is coupled to ground, and wherein the drain presents an inverted input signal;
• a first p-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the first n-channel transistor, and wherein the drain is coupled to the drain of the second n-channel transistor;
• and
• a second p-channel transistor having a gate, a drain, and a source, wherein the gate is receptive to an enabling signal, wherein the source is coupled to a voltage supply, wherein the drain is coupled to the source of the first p-channel transistor.

An input buffer for a low-voltage flash memory device, comprising:

• an input stage having a first n-channel transistor that includes a gate, a drain, and a source, wherein the gate is receptive to an inhibiting signal, wherein the drain is receptive to an input signal, wherein the input stage inhibits the input signal from being presented at the source when the inhibiting signal is at a low level;
• an output stage to present the input signal to the low-voltage flash memory device, wherein the output stage includes:
• a second n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the first n-channel transistor, wherein the source is coupled to ground, and wherein the drain presents an inverted input signal;
• a first p-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the first n-channel transistor, and wherein the drain is coupled to the drain of the second n-channel transistor;
• and
• a second p-channel transistor having a gate, a drain, and a source, wherein the gate is receptive to an enabling signal, wherein the source is coupled to a voltage supply, wherein the drain is coupled to the source of the first p-channel transistor;
• a voltage sensor to trigger when the input signal is at a first high level, wherein the voltage sensor is receptive to a pumped signal and the input signal to produce a sensed signal;
• and
• an inhibiting circuit to selectively produce the inhibiting signal, wherein the inhibiting circuit is receptive to the pumped signal and the sensed signal.

A method for buffering a low-voltage flash memory device, comprising:

• transferring by an input stage having a first n-channel transistor that includes a gate, a drain, and a source, wherein the gate is receptive to an inhibiting signal, wherein the drain is receptive to an input signal, wherein transferring includes inhibiting the input signal from being presented at the source when the inhibiting signal is at a low level;
• outputting by an output stage to present the input signal to the low-voltage flash memory device, wherein outputting includes:
• receiving the input signal by a second n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the first n-channel transistor, wherein the source is coupled to ground, and wherein the drain presents the input signal at a low level when the gate receives the input signal at a high level;
• receiving the input signal by a first p-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the first n-channel transistor, and wherein the drain presents the input signal at a high level when the gate receives the input signal at a low level;
• and
• enabling the first p-channel transistor by a second p-channel transistor having a gate, a drain, and a source, wherein the gate is receptive to a low enabling signal, wherein the source is coupled to a voltage supply, wherein the drain is coupled to the source of the first p-channel transistor.

A method for buffering a low-voltage flash memory device, comprising:

• transferring by an input stage having a first n-channel transistor that includes a gate, a drain, and a source, wherein the gate is receptive to an inhibiting signal, wherein the drain is receptive to an input signal, wherein the input stage refrains from transferring the input signal from being presented at the source when the inhibiting signal is at a low level;
• outputting by an output stage to present the input signal to the low-voltage flash memory device, wherein the output stage includes:
• a second n-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the first n-channel transistor, wherein the source is coupled to ground, and wherein the drain presents an inverted input signal;
• a first p-channel transistor having a gate, a drain, and a source, wherein the gate is coupled to the source of the first n-channel transistor, and wherein the drain is coupled to the drain of the second n-channel transistor;
• and
• a second p-channel transistor having a gate, a drain, and a source, wherein the gate is receptive to an enabling signal, wherein the source is coupled to a voltage supply, wherein the drain is coupled to the source of the first p-channel transistor;
• sensing by a voltage sensor to trigger when the input signal is at a first high level, wherein the voltage sensor is receptive to a pumped signal and the input signal to produce a sensed signal;
• and
• producing by an inhibiting circuit that selectively produces the inhibiting signal, wherein the inhibiting circuit is receptive to the pumped signal and the sensed signal.

A wireless device, comprising:

• a processor;
• a display;
• and
• a low-voltage flash memory device that includes:
• a multiple of thin gate-oxide transistors;
• and
• an input buffer receptive to an enabling signal, an input signal, and an inhibiting signal, wherein the input buffer includes a component that inhibits semiconductor breakdown of the multiple of thin gate-oxide transistors when the inhibiting signal is at a predetermined level.

An input buffer protection circuit comprising:

• an input node to receive an input signal;
• an internal signal node coupled to communicate the input signal to an input buffer circuit;
• a pass transistor coupled between the input node and the internal signal node;
• a bias circuit coupled to the internal signal node, wherein the bias circuit and the pass transistor are coupled to be controlled by an inhibitor signal such that the bias circuit is active to bias the internal signal node to a predetermined voltage while the pass transistor is deactivated to interrupt a signal path from the input node to the internal signal node;
• and
• control circuitry to provide the inhibitor signal.

An integrated circuit comprising:

• an input node to receive an input signal;
• an internal signal node coupled to communicate the input signal to an input buffer circuit;
• a pass transistor coupled between the input node and the internal signal node;
• a bias circuit coupled to the internal signal node, wherein the bias circuit and the pass transistor are coupled to be controlled by an inhibitor signal such that the bias circuit is active to bias the internal signal node to a predetermined voltage while the pass transistor is deactivated to interrupt a signal path from the input node to the internal signal node;
• and
• control circuitry to provide the inhibitor signal to activate the pass transistor and deactivate the bias circuit while the input signal is less than a predetermined threshold voltage level, and to deactivate the pass transistor and activate the bias circuit when the input signal reaches the predetermined threshold voltage level.

A memory device comprising:

• an input node to receive an input signal;
• an internal signal node coupled to communicate the input signal to an input buffer circuit;
• a pass transistor coupled between the input node and the internal signal node;
• a bias circuit coupled to the internal signal node, wherein the bias circuit and the pass transistor are coupled to be controlled by an inhibitor signal such that the bias circuit is active to bias the internal signal node to a predetermined voltage while the pass transistor is deactivated to interrupt a signal path from the input node to the internal signal node;
• and
• control circuitry to provide the inhibitor signal to activate the pass transistor and deactivate the bias circuit while the memory device is in a non-test operation, and to deactivate the pass transistor and activate the bias circuit when the memory device is in a test mode indicated by an elevated voltage greater than a predetermined threshold voltage level provided on the input node.

A method of operating an input buffer comprising:

• receiving an input signal at an input node;
• communicating the input signal to an input buffer circuit through an internal signal node;
• controlling a pass transistor coupled between the input node and the internal signal node and a bias circuit coupled to the internal signal node with an inhibitor signal to activate the bias circuit to bias the internal signal node to a predetermined voltage while the pass transistor is deactivated to interrupt a signal path from the input node to the internal signal node;
• and
• providing the inhibitor signal from control circuitry.

A method of operating an integrated circuit comprising:

• receiving an input signal at an input node;
• communicating the input signal to an input buffer circuit through an internal signal node;
• controlling a pass transistor coupled between the input node and the internal signal node and a bias circuit coupled to the internal signal node with an inhibitor signal to activate the bias circuit to bias the internal signal node to a predetermined voltage while the pass transistor is deactivated to interrupt a signal path from the input node to the internal signal node;
• and
• providing the inhibitor signal from control circuitry to activate the pass transistor and deactivate the bias circuit while the input signal is less than a predetermined threshold voltage level, and to deactivate the pass transistor and activate the bias circuit when the input signal reaches the predetermined threshold voltage level.

A method of operating a memory device comprising:

• receiving an input signal at an input node;
• communicating the input signal to an input buffer circuit through an internal signal node;
• controlling a pass transistor coupled between the input node and the internal signal node and a bias circuit coupled to the internal signal node with an inhibitor signal to activate the bias circuit to bias the internal signal node to a predetermined voltage while the pass transistor is deactivated to interrupt a signal path from the input node to the internal signal node;
• and
• providing the inhibitor signal from control circuitry to activate the pass transistor and deactivate the bias circuit while the memory device is in a non-test operation, and to deactivate the pass transistor and activate the bias circuit when the memory device is in a test mode indicated by an elevated voltage greater than a predetermined threshold voltage level provided on the input node.

An input system for a low-voltage flash memory device, comprising:

• an input buffer comprising:
• an input stage comprising a transistor comprising a gate, a drain, and a source, the gate being coupled to receive an inhibiting signal and the drain being coupled to receive an input signal, the transistor being controlled to inhibit the input signal from being presented at the source when the inhibiting signal is at a first predetermined level;
• and
• an output stage coupled to the input stage to present the input signal to the low-voltage flash memory device;
• and
• a voltage sensor coupled to receive the input signal and a pumped signal to trigger when the input signal is at a second predetermined level.

An input system for a low-voltage flash memory device, comprising:

• an input buffer comprising:
• an input stage comprising a transistor comprising a gate, a drain, and a source, the gate being coupled to receive an inhibiting signal and the drain being coupled to receive an input signal, the transistor being controlled to inhibit the input signal from being presented at the source when the inhibiting signal is at a first predetermined level;
• and
• an output stage coupled to the input stage to present the input signal to the low-voltage flash memory device;
• and
• an inhibiting circuit coupled to the input buffer to selectively produce the inhibiting signal, the inhibiting circuit being coupled to receive a pumped signal and a sensed signal.