Method of retaining memory state in a programmable conductor RAM

A memory cell comprising:

• a chalcogenide glass element;
• first and second electrodes connected to said chalcogenide glass element;
• a first voltage source for applying a programming voltage across said first and second electrodes to program said cell from a first stored state to a second stored state;
• and
• a second voltage source for applying a stabilizing voltage across said first and second electrodes to maintain said second stored state.

A memory cell comprising:

• a chalcogenide glass element;
• first and second electrodes connected to said chalcogenide glass element;
• a first voltage source for applying a programming voltage of at least 0.25 volts across said first and second electrodes to program said cell from a first stored state to a second stored state;
• and
• a second voltage source for applying a stabilizing voltage between about 0.09 and 0.13 volts across said first and second electrodes to maintain said second stored state.

A method for operating a non-volatile chalcogenide memory cell, comprising the steps of:

• programming said cell to a predetermined state with a voltage of at least 0.25 volts;
• applying a stabilizing voltage to said cell at between about 0.09 and about 0.13 volts;
• and
• reading said cell by applying a voltage of from greater than about 0 volts to about 0.13 volts to said cell.

A method for operating non-volatile chalcogenide memory cells in an array, comprising the steps of:

• programming selected memory cells of said array with a voltage of at least about 0.25 volts;
• maintaining a programmed state of said selected memory cells by applying a stabilizing voltage between about 0.09 and about 0.13 volts to said array;
• and
• reading said array by applying a voltage of from greater than about 0 volts to about 0.13 volts to said array.

A programmable conductor random access memory device comprising:

• a chalcogenide glass element;
• first and second electrodes connected to said chalcogenide glass element;
• a first voltage source for applying a programming voltage across said first and second electrodes to program said device from a first stored state to a second stored state;
• a second voltage source for applying a stabilizing voltage across said first and second electrodes to maintain said second stored state, wherein said second voltage is less than said fist voltage;
• and
• a third voltage source for applying a read-out voltage across said first and second electrodes to read data out of said device.

A memory cell comprising:

• a first voltage source for applying a programming voltage across first and second electrodes to program said cell from a first stored state to a second stored state;
• a second voltage source for applying a read-out voltage across said first and second electrodes to maintain said second stored state;
• and
• a third voltage source for applying an erase voltage across said first and second electrodes to erase said memory cell, wherein said readout voltage has a value less than said programming voltage value.

A memory cell comprising:

• a first voltage source for applying a programming voltage of at least 0.25 volts across first and second electrodes to program said cell from a first stored state to a second stored state;
• a second voltage source for applying a stabilizing voltage between about 0.09 and 0.13 volts across said first and second electrodes to maintain said second stored state;
• and
• a third voltage source for applying a read-out voltage from about 0 volts to about 0.13 volts across said first and second electrodes to read-out said cell.

A programmable conductor random access memory device comprising:

• a chalcogenide glass element;
• first and second electrodes connected to said chalcogenide glass element;
• a first voltage source for applying a programming voltage of at least 0.25 volts across said first and second electrodes to program said device from a first stored state to a second stored state;
• a second voltage source for applying a stabilizing voltage between about 0.09 and 0.13 volts across said first and second electrodes to maintain said second stored state;
• and
• a third voltage source for applying a read-out voltage from about 0 volts to about 0.13 volts across said first and second electrodes to read-out said device.

A memory cell comprising:

• a chalcogeride glass element;
• first and second electrodes connected to said chalcogenide glass element;
• a first voltage source for applying a programming voltage across said first and second electrodes to program said cell from a first stored state to a second stored state;
• and
• a second voltage source for applying a read-out voltage across said first and second electrodes to maintain said second stored state.

A method for operating a non-volatile chalcogenide memory cell, comprising the steps of:

• programming said cell to a predetermined state with a voltage of at least 0.25 volts;
• reading said cell by applying a read-out voltage to said cell at between about 0.09 and about 0.13 volts, wherein said read-out voltage stabilizes said cell;
• and
• erasing said cell by applying a voltage between about 0 and about −1 volts.

A method for operating a non-volatile chalcogenide memory cell, comprising the steps of:

• programming said cell to a predetermined state with a voltage of at least 0.25 volts;
• applying a stabilizing voltage to said cell at between about 0.09 and about 0.13 volts;
• and
• erasing said cell by applying a voltage between about 0 and about −1 volts.

A method for operating a non-volatile chalcogenide memory cell, comprising the steps of:

• programming said cell by applying a first voltage to said cell;
• stabilizing said cell by applying a second voltage to said cell, which is less than said first voltage;
• reading said cell by applying a third voltage to said cell, wherein said third voltage is less than said second voltage;
• and
• erasing said cell by applying a fourth voltage to said cell, which is less than said third voltage.

A memory cell comprising:

• a chalcogenide glass element;
• first and second electrodes connected to said chalcogenide glass element;
• a first voltage source for applying a programming voltage across said first and second electrodes to program said cell from a first stored state to a second stored state;
• a second voltage source for applying a read-out voltage across said first and second electrodes to maintain said second stored state;
• and
• a third voltage source for applying an erase voltage across said first and second electrodes to erase said memory cell.

A memory cell comprising:

• a first voltage source for applying a programming voltage of at least 0.25 volts across first and second electrodes to program said cell from a first stored state to a second stored state;
• a second voltage source for applying a stabilizing voltage between about 0.09 and 0.13 volts across said first and second electrodes to maintain said second stored state;
• a third voltage source for applying a read-out voltage from about 0 volts to about 13 volts across said first and second electrodes to read-out said cell;
• and
• a fourth voltage source for applying an erase voltage from about 0 volts to about −1 volts.

A memory cell comprising:

• a chalcogenide glass element;
• first and second electrodes connected to said chalcogenide glass element;
• a first voltage source for applying a programming voltage of at least 0.25 volts across said first and second electrodes to program said cell from a first stored state to a second stored state;
• a second voltage source for applying a stabilizing voltage between about 0.09 and 0.13 volts across said first and second electrodes to maintain said second stored state;
• a third voltage source for applying a read-out voltage from about 0 volts to about 0.13 volts across said first and second electrodes to read-out said cell;
• and
• a fourth voltage source for applying an erase voltage from about 0 volts to about −1 volts across said first and second electrodes to erase said cell.