Electrostatic discharge protection device for mixed voltage interface
AssigneeIndustrial Technology Research Institute
InventorsMing-Dou Ker, Kuo-Chun Hsu, Hsin-Chin Jiang
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AssigneeIndustrial Technology Research Institute
InventorsMing-Dou Ker, Kuo-Chun Hsu, Hsin-Chin Jiang
Estimating the term…
An electrostatic discharge protection circuit that includes at least two transistors connected in a stacked configuration, a first diffusion region of a first dopant type shared by two adjacent transistors, and a second diffusion region of a second dopant type formed in the first diffusion region. A substrate-triggered site is induced into the device structure of the stacked transistors to improve ESD robustness and turn-on speed. An area-efficient layout to realize the stacked transistors is proposed. The stacked transistors may be implemented in ESD protection circuits with a mixed-voltage I/O interface, or in integrated circuits with multiple power supplies. The stacked transistors are fabricated without using a thick-gate mask.
An electrostatic discharge protection circuit device, comprising:
An integrated circuit device for electrostatic protection, comprising:
An integrated circuit for electrostatic discharge protection in a mixed voltage interface, comprising:
A method for protecting a mixed voltage interface from electrostatic discharge, comprising:
Dependencies are inferred from the claim text.