Display driver circuit and display device

A display driver circuit which drives signal electrodes of a display device based on gray-scale data, comprising:

• first to (M+N)th (M and N are positive integers) shift register blocks;
• a clock input control circuit which controls input of a clock signal which is supplied to each of the first to (M+N)th shift register blocks and determines shift timing;
• first to (M+N)th clock mask circuits which generate first to (M+N)th clock signals by performing mask control for the clock signal supplied to the first to (M+N)th shift register blocks and output the first to (M+N)th clock signals;
• and
• a signal electrode driver circuit which drives the signal electrodes by using drive voltages corresponding to first to (M+N)th gray-scale data, the first to (M+N)th gray-scale data being held in the first to (M+N)th shift register blocks,
• wherein the first to Mth shift register blocks are disposed in a region on a first direction side of the clock input control circuit, shift a given data enable signal input to the first shift register block based on the first to Mth clock signals and output the shifted data enable signal to a shift register block adjacent in a second direction opposite to the first direction, and hold the first to Mth gray-scale data based on the shifted data enable signal,
• wherein the (M+1)th to (M+N)th shift register blocks are disposed in a region on the second direction side of the clock input control circuit, shift a data enable signal input to the (M+1)th shift register block from the Mth shift register block based on the (M+1)th to (M+N)th clock signals and output the shifted data enable signal to a shift register block adjacent in the second direction, and hold the (M+1)th to (M+N)th gray-scale data based on the shifted data enable signal,
• wherein the first to Mth clock mask circuits are connected in the second direction in order from the first to Mth clock mask circuit and mask the first to Mth clock signals in order from the first to Mth clock mask circuit, and
• wherein the (M+1)th to (M+N)th clock mask circuits are connected in the second direction in order from the (M+1)th to (M+N)th clock mask circuit and unmask the (M+1)th to (M+N)th clock signals in order from the (M+1)th to (M+N)th clock mask circuit.

A display driver circuit which drives signal electrodes of a display device based on gray-scale data, comprising:

• first to Mth (M is a positive integer) shift register blocks;
• a data input control circuit which controls input of the gray-scale data supplied to the first to Mth shift register blocks;
• first to Mth data mask circuits which generate first to Mth gray-scale data by performing mask control for the gray-scale data supplied to the first to Mth shift register blocks and output the first to Mth gray-scale data, first to Mth gray-scale data being held in the first to Mth shift register blocks;
• and
• a signal electrode driver circuit which drives the signal electrodes by using drive voltages corresponding to the first to Mth gray-scale data,
• wherein the first to Mth shift register blocks are disposed in a region on a first direction side of the data input control circuit, shift a given data enable signal input to the first shift register block and output the shifted data enable signal to a shift register block adjacent in a second direction opposite to the first direction, and hold the first to Mth gray-scale data, for which mask control is performed by the first to Mth data mask circuits, based on the shifted data enable signal, and
• wherein the first to Mth data mask circuits are connected in the second direction in order from the first to Mth data mask circuit and mask the first to Mth gray-scale data in order from the first to Mth data mask circuit.

A display driver circuit which drives signal electrodes of a display device based on gray-scale data, comprising:

• first to Nth (N is a positive integer) shift register blocks;
• a data input control circuit which controls input of the gray-scale data supplied to the first to Nth shift register blocks;
• first to Nth data mask circuits which generate first to Nth gray-scale data by performing mask control for the gray-scale data supplied to the first to Nth shift register blocks and output the first to Nth gray-scale data, the first to Nth gray-scale data being held in the first to Nth shift register blocks;
• and
• a signal electrode driver circuit which drives the signal electrodes by using drive voltages corresponding to the first to Nth gray-scale data,
• wherein the first to Nth shift register blocks are disposed in a region on a second direction side of the data input control circuit, shift a given data enable signal input to the first shift register block and output the shifted data enable signal to a shift register block adjacent in the second direction, and hold the first to Nth gray-scale data, for which mask control is performed by the first to Nth data mask circuits, based on the shifted data enable signal, and
• wherein the first to Nth data mask circuits are connected in the second direction in order from the first to Nth data mask circuit and unmask the first to Nth gray-scale data in order from the first to Nth data mask circuit.

A display driver circuit which drives signal electrodes of a display device based on gray-scale data, comprising:

• first to Mth (M is a positive integer) shift register blocks;
• a clock input control circuit which controls input of a clock signal which is supplied to each of the first to Mth shift register blocks and determines shift timing;
• first to Mth clock mask circuits which generate first to Mth clock signals by performing mask control for the clock signal supplied to the first to Mth shift register blocks and output the first to Mth clock signals;
• and
• a signal electrode driver circuit which drives the signal electrodes by using drive voltages corresponding to first to Mth gray-scale data,
• wherein the first to Mth shift register blocks are disposed in a region on a first direction side of the clock input control circuit, shift a given data enable signal input to the first shift register block based on the first to Mth clock signals and output the shifted data enable signal to a shift register block adjacent in a second direction opposite to the first direction, and hold the first to Mth gray-scale data based on the shifted data enable signal, and
• wherein the first to Mth clock mask circuits are connected in the second direction in order from the first to Mth clock mask circuit and mask the first to Mth clock signals in order from the first to Mth clock mask circuit.

A display driver circuit which drives signal electrodes of a display device based on gray-scale data, comprising:

• first to Nth (N is a positive integer) shift register blocks;
• a clock input control circuit which controls input of a clock signal which is supplied to each of the first to Nth shift register blocks and determines shift timing;
• first to Nth clock mask circuits which generate first to Nth clock signals by performing mask control for the clock signal supplied to the first to Nth shift register blocks and output the first to Nth clock signals;
• and
• a signal electrode driver circuit which drives the signal electrodes by using drive voltages corresponding to first to Nth gray-scale data,
• wherein the first to Nth shift register blocks are disposed in a region on a second direction side of the clock input control circuit, shift a given data enable signal input to the first shift register block based on the first to Nth clock signals and output the shifted data enable signal to a shift register block adjacent in the second direction, and hold the first to Nth gray-scale data based on the shifted data enable signal, and
• wherein the first to Nth clock mask circuits are connected in the second direction in order from the first to Nth clock mask circuit and unmask the first to Nth clock signals in order from the first to Nth clock mask circuit.