Bulk node biasing method and apparatus

A circuit to isolate an input voltage and an output voltage and transfer charge from a charge pumping voltage booster to an output voltage load, said circuit comprising:

• a pass gate including an input terminal, an output terminal, a gate control terminal and a bulk node;
• a biasing circuit for selecting a bulk node biasing voltage for said pass gate from among said input voltage and said output voltage, including:
• a first switch having a first switch terminal for coupling to said input voltage and a second switch terminal for coupling to said bulk node of said pass gate, said first switch further including a control terminal for coupling to said output voltage, said control terminal responsive to an applied voltage to enable conduction between said first switch terminal and said second switch terminal of said first switch;
• and
• a second switch having a first switch terminal for coupling to said bulk node of said pass gate and a second switch terminal for coupling to said output voltage, said second switch further including a control terminal for coupling to said input voltage, said control terminal responsive to an applied voltage to enable conduction between said first switch terminal and said second switch terminal of said second switch.

A charge pump for converting an input voltage to an output voltage of a different magnitude or polarity, comprising:

• a voltage booster for coupling to said input voltage for switching stored charge to said different magnitude or polarity from said input voltage;
• a pass gate for providing isolation between said input voltage and said output voltage, said pass gate coupled to said voltage booster at an input terminal of said pass gate, said pass gate further including an output terminal, a gate terminal, and a bulk node;
• and
• a biasing circuit for selecting a bulk node biasing voltage for said pass gate from among said input voltage and said output voltage, including:
• a first switch having a first switch terminal for coupling to said input voltage and a second switch terminal for coupling to said bulk node of said pass gate, said first switch further including a control terminal for coupling to said output voltage, said control terminal responsive to an applied voltage to enable conduction between said first switch terminal and said second switch terminal of said first switch;
• and
• a second switch having a first switch terminal for coupling to said bulk node of said pass gate and a second switch terminal for coupling to said output voltage, said second switch further including a control terminal for coupling to said input voltage, said control terminal responsive to an applied voltage to enable conduction between said first switch terminal and said second switch terminal of said second switch.

A charge pump, comprising:

• a voltage booster responsive to an input voltage for switching stored charge from said input voltage to a boosted voltage of a different magnitude or polarity from said input voltage;
• a pass gate coupled at an input terminal to receive said boosted voltage of said voltage booster and to isolate and transfer said boosted voltage to an output terminal of said pass gate as an output voltage of said charge pump when switched in response to a pass gate control signal at a gate terminal of said pass gate;
• and
• a biasing circuit coupled to said boosted voltage and said output voltage of said charge pump for biasing a bulk node of said pass gate with a potential comprising the greater of a potential of said boosted voltage and a potential of said output voltage.

A charge pump, comprising:

• a plurality of voltage boosters responsive to an input voltage for switching stored charge from said input voltage to an individual one of a respective plurality of boosted voltages of a different magnitude or polarity from said input voltage;
• a corresponding plurality of pass gates, each respectively coupled to said plurality of voltage boosters to individually receive a respective one of said plurality of boosted voltages and to isolate and transfer said plurality of boosted voltages to an individual corresponding output terminal of said plurality of pass gates as a unified output voltage of said charge pump in response to at least one pass gate control signal coupled to an individually corresponding plurality of pass gate control terminals;
• and
• a corresponding plurality of biasing circuits, each individually coupled to said plurality of boosted voltages and said output voltage of said charge pump for biasing an individually respective plurality of bulk nodes of said plurality of pass gates with a greater potential of either said respective one of said plurality of boosted voltages or said output voltage.

An integrated memory device comprising:

• an array of memory cells operative with a first voltage and a second voltage different in magnitude or polarity from said first voltage;
• and
• a charge pump coupled to at least a portion of said array of memory cells to generate said second voltage from said first voltage, said charge pump including:
• a voltage booster responsive to said first voltage for switching stored charge from said first voltage to a boosted voltage of a different magnitude or polarity from said first voltage;
• a pass gate coupled at an input terminal to receive said boosted voltage of said voltage booster and to isolate and transfer said boosted voltage to an output terminal of said pass gate as a second voltage of said charge pump when switched in response to a pass gate control signal at a gate terminal of said pass gate;
• and
• a biasing circuit coupled to said boosted voltage and said second voltage of said charge pump for biasing a bulk node of said pass gate with the greater potential of either said boosted voltage or said second voltage.

A computer system, comprising:

• a processor;
• and
• a memory system operably coupled to said processor including:
• an array of memory cells operative with a first voltage and a second voltage different in magnitude or polarity from said first voltage;
• and
• a charge pump coupled to at least a portion of said array of memory cells to generate said second voltage from said first voltage, said charge pump including a biasing circuit for biasing a bulk node of a pass gate used to isolate and transfer charge from said first voltage to form said second voltage, said biasing circuit configured for biasing a bulk node of said pass gate with the greater of a potential at an input terminal and a potential at an output terminal of said pass gate.

An integrated circuit comprising:

• a circuit operative with a first voltage and a second voltage different in magnitude or polarity from said first voltage;
• and
• a charge pump coupled to at least a portion of said circuit to generate said second voltage from said first voltage, said charge pump including:
• a voltage booster responsive to said first voltage for switching stored charge from said first voltage to a boosted voltage of a different magnitude or polarity from said first voltage;
• a pass gate coupled at an input terminal to receive said boosted voltage of said voltage booster and to isolate and transfer said boosted voltage to an output terminal of said pass gate as a second voltage of said charge pump when switched in response to a pass gate control signal at a gate terminal of said pass gate;
• and
• a biasing circuit coupled to said boosted voltage and said second voltage of said charge pump for biasing a bulk node of said pass gate with a greater of a potential of said boosted voltage and a potential of said second voltage.

An integrated circuit, comprising:

• a first circuit portion operative on a first voltage;
• a second circuit portion operative on a second voltage;
• and
• a charge pump operably coupled to said first circuit portion and said second circuit portion, said charge pump configured for generating said second voltage from said first voltage, including:
• a voltage booster responsive to said first voltage for switching stored charge from said first voltage to a boosted voltage of a different magnitude or polarity from said first voltage;
• a pass gate coupled at an input terminal to receive said boosted voltage of said voltage booster and to isolate and transfer said boosted voltage to an output terminal of said pass gate as a second voltage of said charge pump when switched in response to a pass gate control signal at a gate terminal of said pass gate;
• and
• a biasing circuit coupled to said boosted voltage and said second voltage of said charge pump for biasing a bulk node of said pass gate with a greater of a potential of said boosted voltage and a potential of said second voltage.

A method of biasing a bulk node of a pass gate in a charge pump, the method comprising:

• monitoring first and second voltages at input and output terminals, respectively, of said pass gate;
• selecting one of said first and second voltages having a greater potential;
• and
• coupling said one of said first and second voltages having a greater potential to said bulk node of said pass gate of said charge pump.