Structures of vertical resistors and FETs as controlled by electrical field penetration and a band-gap voltage reference using vertical FETs operating in accumulation through the field penetration effect

A vertical resistor structure, comprising:

• two shallow trench isolation (STI) structures deposited in a well of a first conductivity type;
• a channel region formed between said two STI structures, said channel region having a parasitic resistance;
• a lightly doped drain (ldd) junction of said first conductivity type deposed on top of said channel region to form a contact with said channel region;
• one or more control junctions of a second conductivity type butting against that side of each of said STI structures not in contact with said channel region, where said control junction may further surround said channel region;
• and
• said well coupled to a voltage source return.

A vertical variable resistor, comprising:

• two shallow trench isolation (STI) structures deposited in a well of a first conductivity type;
• a channel region formed between said two STI structures, said channel region having a parasitic resistance;
• a lightly doped drain (ldd) junction of said first conductivity type deposed on top of said channel region to form a contact with said channel region.
• at least one control junction of a second conductivity type butting against that side of each of said STIs not in contact with said channel region, said control junction coupled to a first voltage source, said control junction inducing an STI field penetration effect in said channel region;
• said ldd junction coupled to a second voltage source;
• and
• said well coupled to a voltage source return.

A structure for a vertical field effect transistor (FET), comprising:

• two shallow trench isolation (STI) structures deposited in a well of a first conductivity type;
• a channel region formed between said two STI structures, said channel region having a parasitic resistance;
• a lightly doped drain (ldd) junction of said first conductivity type deposed on top of said channel region to form a contact with said channel region;
• a base of a second conductivity type deposited on one side of each of said STI structures, said base in contact with that side of said STI structure not in contact with said channel region;
• and
• at least one control junction of a second conductivity type butting against that side of each of said STI structures not in contact with said channel region, where each of said control junctions is in contact with one of said bases.

A vertical field effect transistor (FET), comprising:

• two shallow trench isolation (STI) structures deposited in a well of a first conductivity type;
• a channel region formed between said two STI structures, said channel region having a vertical parasitic resistance;
• a lightly doped drain (ldd) junction of said first conductivity type deposed on top of said channel region to form a contact with said channel region;
• a base of a second conductivity type deposited on one side of each of said STI structures, said base in contact with that side of said STI structure not in contact with said channel region;
• and
• one or more control junctions of said second conductivity type butting against that side of each of said STI structures not in contact with said channel region, where each of said control junctions is in contact with said base, where the field penetration effect of said control junctions, when biased, modulates said vertical parasitic resistance of said channel region.

A band-gap reference circuit using vertical field effect transistors (FETs), comprising:

• three shallow trench isolation (STI) structures deposited in a well of a first conductivity type;
• first and a second channel regions formed between said three STI structures, such that there is one inner and two outer STIs, where said first and second channel region together with said inner and an outer STIs comprise a first and a second vertical FET, respectively, said channel regions having a parasitic resistance;
• a lightly doped drain (ldd) junction of said first conductivity type deposed on top of each of said channel regions to form contacts with said channel regions;
• a control junction of first and second conductivity type each, butting against said outer STIs, respectively, where said first and said second control junction function as gates for said first and said second vertical FET, respectively;
• and
• a base of a second conductivity type buried in said well, said well in contact with said control junction and the lower part of one of said outer STIs.

A band-gap reference circuit using vertical n-field effect transistors (n-FETs), comprising:

• three shallow trench isolation (STI) structures deposited in an n-well of a first conductivity type;
• first and a second channel regions formed between said three STI structures, such that there is one inner and two outer STIs, where said first and second channel region together with said inner and an outer STIs constitute a first and a second vertical n-FET, respectively, said channel regions having a parasitic resistance;
• a p-lightly doped drain (pldd) junction deposited on top of each of said channel regions to form contacts with said channel regions;
• an n+ control junction butting against one of said outer STIs, where said n+ control junction functions as a gate for said first vertical n-FET;
• a p+ control junction butting against the other of said outer STIs, where said p+ control junction functions as a gate for said second vertical n-FET;
• and
• a p-base buried in said n-well, said p-base in contact with said n+ control junction and the lower part of said one outer STI.

A band-gap reference circuit using vertical p-field effect transistors (p-FETs), comprising:

• three shallow trench isolation (STI) structures deposited in a p-well.
• a first and a second channel regions formed between said three STI structures, such that there is one inner and two outer STIs, where said first and second channel region together with said inner and an outer STIs constitute a first and a second vertical p-FET, respectively, said channel regions having a parasitic resistance;
• an n-lightly doped drain (nldd) junction deposited on top of each of said channel regions to form contacts with said channel regions;
• a p+ control junction butting against one of said outer STIs, where said p+ control junction functions as a gate for said first vertical p-FET;
• an n+ control junction butting against the other of said outer STIs, where said n+ control junction functions as a gate for said second vertical p-FET;
• and
• an n-base buried in said p-well, said n-base in contact with said p+ control junction and the lower part of said one outer STI.

A method of fabricating vertical resistors, comprising the steps of:

• a) STI isolation formation:
• Cleaning, pad-oxide growing, depositing Si3N4;
• AA masking, trench etching, cleaning;
• Deep trench masking, deep trench etching;
• Liner oxidation, HDP CVD oxide depositing, RTA densify;
• Oxide CM polishing, Si3N4 removing;
• b) Transistor formation:
• p-well (1) masking, implanting;
• p-well (2) masking, implanting;
• n-well (1) masking, implanting;
• n-well (2) masking, implanting;
• resistor (p-type) area masking and implanting;
• resistor (n-type) area masking and implanting;
• c) Gate formation:
• 1st gate-oxidation;
• Dual gate-oxide masking, wet oxide dipping;
• Cleaning, 2nd gate-oxidation, depositing undoped Poly;
• gate masking, poly etching, cleaning, poly-oxidation;
• d) Transistor formation:
• nldd-1 masking, implanting;
• pldd-1 masking, implanting;
• pldd-2 masking, implanting;
• nldd-2 masking, implanting;
• Liner-oxidation, depositing gate spacer (SiN, Teox);
• Gate spacer oxide/SiN etching, cleaning;
• n+ S/D and p+ S/D, masking, implanting;
• deep n+ masking and implanting;
• deep p+ masking and implanting;
• e) Salicide and contact:
• Co depositing, TiN depositing, RT Annealing-1, Co stripping, RT Annealing-2;
• SiN depositing, PSG depositing, ILD CMP polishing;
• Contact masking, contact oxide etching;
• W-CVD depositing, W-CMP polishing;
• and
• f) Continuing with BEOL metal interconnecting.