Providing high precision resistance in an integrated circuit using a thin film resistor of controlled dimension

A method for constructing a thin film resistor for an integrated circuit, comprising:

• forming a stencil structure on a substrate surface, the stencil structure comprising one or more layers and defining a channel separating first and second opposing portions of the stencil structure;
• depositing a thin film resistor material, some of the thin film resistor material being deposited on the substrate surface within the channel to define the thin film resistor, some of the thin film resistor material being deposited outside the channel on the first and second opposing portions of the stencil structure, the thin film resistor having an initial width determined by a width of the channel;
• depositing a planarizing material within the channel so as to substantially surround the thin film resistor within the channel and protect against reduction of the initial width of the thin film resistor during subsequent process steps for removing the stencil structure from the substrate surface;
• removing at least some of the planarizing material sufficient to expose the thin film resistor material deposited outside the channel on the first and second opposing portions of the stencil structure, the thin film resistor within the channel remaining covered by the planarizing material;
• removing the thin film resistor material deposited outside the channel on the first and second opposing portions of the stencil structure;
• removing the first and second opposing portions of the stencil structure;
• and
• removing the remaining planarizing material deposited on the thin film resistor within the channel.

An integrated circuit, comprising:

• a thin film resistor comprising a thin film resistor material that has been deposited on a substrate surface within a channel defined by opposing first and second portions of a stencil structure formed on the substrate surface, the thin film resistor material having an initial width determined by a width of the channel, the thin film resistor material having been deposited using first collimated beams comprising the thin film resistor material and directed substantially perpendicular to the substrate surface, the stencil structure having been adapted to receive a planarizing material so as to substantially surround the thin film resistor material within the channel and protect against reduction of the initial width of the thin film resistor material during subsequent process steps for removing the stencil structure from the substrate surface, the presence of the planarizing material allowing the stencil structure to be removed from the substrate surface using standard wet etch techniques while substantially preventing etch-back or undercutting of the thin film resistor material;
• a head mask material overlaying an end portion of the thin film resistor;
• a hard mask material covering the end portion of the thin film resistor and underlying the head mask material, the hard mask material having been initially deposited on substantially all of the thin film resistor material within the channel to protect against diffusion of the head mask material into the thin film resistor during operation of the integrated circuit, the hard mask material having been deposited using second collimated beams comprising the hard mask material and directed substantially perpendicular to the substrate surface;
• a dielectric material overlaying the head mask material and defining a via formed in the dielectric material above a portion of the head mask material;
• and
• a conductive material deposited in the via and coupled to the portion of the head mask material, the conductive material electrically connecting the thin film resistor to one or more other components of the integrated circuit.