Double sided IGBT phase leg architecture and clocking method for reduced turn on loss

The circuit of claiml wherein the second DIGBT performs a transistor switching function, and the first DIGBT performs a freewheeling diode function, wherein the second DIGBT's primary gate is being turned on and off, and during the switching cycle of the second DIGBT the secondary gate of the first DIGBT remains on which enables the first DIGBT to perform the freewheeling function in the circuit.

An asymmetric DIGBT comprising:

• A N type semiconductor substrate forming a first and second N drain, a P type region adjacent to each side of the first and-second N drain regions forming a P+ type body, a N+ type source formed on the surface of each P+ type body, a first and second oxide gate formed on each of the N drain regions, overlapping a portion of the P+ type body and extending to overlap a portion of the N+ source, a dielectric material insulating to top of each of the oxide gate, a first surface metal adjacent to the dielectric material insulating the first oxide gate, overlapping the N+ source and extending to the exposed region of the P+ body forming a first surface junction, a second surface metal adjacent to the dielectric material insulating the second oxide gate, overlapping the N+ source and extending to the exposed region of the P+ body forming a second surface junction, wherein said portion of the N type substrate forming the second N drain has a higher N dopant concentration in the central N drain region near the second-surface junction than near the first-surface junction whereby the DIGBT has a low avalanche breakdown voltage in the 3rd quadrant and upon activation of the second gate hole-injection is suppressed efficiently suppressed resulting in less stored charge and reduced turn-off time.