Device and method for detecting alignment of deep trench capacitors and word lines in DRAM devices

A method for detecting alignment of deep trench capacitors and word lines in DRAM devices with vertical transistors, comprising:

• providing a wafer with at least one scribe line region and at least one memory region;
• forming a plurality of memory cells with vertical transistors in the memory region and at least one test device in the scribe line simultaneously, wherein the memory cells have word line areas and deep trench capacitors, the test device including:
• an active area disposed in the scribe line region;
• an H-type deep trench capacitor disposed in the active area, having parallel first and second portions and a third portion, wherein each of the first and second portions has a center and two ends, and the third portion is disposed between the centers of the first and second portions;
• first to fourth conductive pads disposed on the two ends of the first and second portions respectively;
• and
• a bar-type conductive pad disposed between the first and second portions, having a center aligned with a center of the third portion;
• detecting a first resistance between the first conductive pad disposed on the first portion and the bar-type conductive pad, and a second resistance between the second conductive pad disposed on the second portion and the bar-type conductive pad;
• determining alignment of the H-type deep trench capacitor and the bar-type conductive pad according to the first resistance and the second resistance;
• and
• determining alignment of the deep trench capacitors and word lines in the memory regions according to alignment of the H-type deep trench capacitor and the bar-type conductive pad of the test device.