System and method for correlated clock networks

A method for balancing correlated clock networks, the method comprising:

• identifying each clock path within the correlated clock networks that do not have a longest series of non-clock signal delivering logic cells;
• for each identified clock path, adding one or more logic cells to the identified clock path until each active element matches each active element in a path with the longest series of non-clock delivering logic cells;
• and
• setting one or more inputs to the added logic cells to a value that will pass a clock signal.

A method for preventing clock skew and impedance differences affecting a correlated clock network, the method comprising:

• performing a clock balancing for the correlated clock network;
• identifying each related node across a sub-network in the correlated clock network;
• identifying each input driven via the identified related nodes;
• and
• adding one or more active elements to one or more nodes in the identified related nodes until each element in the identified related nodes drives a same number of inputs.

An apparatus configured for clock balancing, the apparatus comprising:

• means in a correlated clock network including a plurality of clock networks, for identifying one or more clock networks of the plurality of clock networks, the one or more clock networks having more active elements as compared to other clock networks of the plurality of clock networks;
• for those identified clock networks, means for identifying a pattern of active elements therein as transversed by a clock signal;
• and
• for those unidentified clock networks in the correlated clock networks, means for adding active elements such that those active elements transversed by a clock signal match those transversed in the clock networks with the most active elements.

A computer-readable medium containing computer-executable instructions to perform a method for clock balancing, the method comprising:

• identifying each clock path within the correlated clock networks that do not have a longest series of non-clock signal delivering logic cells;
• for each identified clock path, adding one or more logic cells to the identified clock path until each active element matches each active element in a path with the longest series of non-clock delivering logic cells;
• and
• setting one or more inputs to the added logic cells to a value that will pass a clock signal.

A computer-readable medium containing computer-executable instructions to perform a method for balancing correlated clock networks, the method comprising:

• in a correlated clock network including a plurality of clock networks, identifying one or more clock networks of the plurality of clock networks, the one or more clock networks having more active elements as compared to other clock networks of the plurality of clock networks;
• for those identified clock networks, identifying a pattern of active elements therein as transversed by a clock signal;
• and
• for those unidentified clock networks in the correlated clock networks, adding active elements such that those added active elements transversed by the clock signal match those transversed in the identified clock networks.

A computer-readable medium containing computer-executable instructions to perform a method for preventing clock skew and impedance differences affecting a correlated clock network, the method comprising:

• performing a clock balancing for the correlated clock network;
• identifying any related nodes in the correlated clock network;
• identifying any inputs driven via one or more of the identified related nodes;
• and
• adding one or more active elements to each of the identified related nodes until each node of the identified related nodes have same inputs attached thereto.

A network synthesis tool for preventing clock skew and impedance differences affecting a correlated clock network, the network synthesis tool comprising:

• a clock balancing module to clock balance the correlated clock network;
• a node identification module to identify any related nodes across a sub-network in the correlated clock network;
• an input identification module to identify each input driven via the identified related nodes;
• and
• an element insertion module to add one or more active elements to one or more nodes in the identified related nodes until each element in the identified related nodes drives a same number of inputs.