Robust delay metric for RC circuits

Abstract

Physical design optimizations for integrated circuits, such as placement, buffer insertion, floorplanning and routing, require fast and accurate analysis of resistive-capacitive (RC) delays in the network. A method is disclosed for estimating delays at nodes in an RC circuit by calculating a first and second impulse response moments of the RC circuit, and matching the impulse response moments to a Weibull distribution. Based on the match, a signal delay value is computed. The invention may thus be used to determine whether the RC circuit meets a desired optimization condition, based on the signal delay value. In the exemplary implementation, the signal delay value at a delay point is calculated by finding a percentile of the Weibull distribution corresponding to the delay point. This implementation is accurate and very efficient as it uses only two very small look-up tables.

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