Correction of spacing violations between pure fill via areas in a multi-wide object class design layout
AssigneeSun Microsystems, Inc.
InventorMu-Jing Li
Life of this patent
Estimating the term…
Abstract
In a Pure Fill Via Area (PFVA) extraction design flow, the extracted PFVAs may violate the minimum via spacing rule with the existing vias and may also violate the minimum via spacing rule among themselves. Such extracted PFVA violations may be corrected in an automatable design flow not requiring user intervention by removing any portion of a PFVA falling within a minimum via spacing rule of an existing via, to form a DRC-clean PFVA relative to existing vias, and removing any portion of a DRC-clean PFVA falling within the minimum via spacing rule of another DRC-clean PFVA.
Claims48
A method for use with a design layout, said method for correcting spacing violations in pure fill via areas (PFVA) for an associated via layer of the design layout, said method comprising the steps of:
- (1) removing any portion of a PFVA falling within a minimum via spacing rule of an existing via on the associated via layer, to form a DRC-clean PFVA relative to existing vias;
- and
- (2) removing any portion of a DRC-clean PFVA falling within the minimum via spacing rule of another DRC-clean PFVA.
A method of processing one or more design files for an electronic circuit, the one or more design files encoding representations of a design layout of the electronic circuit, the design layout comprising pure fill via areas (PFVA) for an associated via layer, said method comprising the steps of:
- (1) removing any portion of a PFVA falling within a minimum via spacing rule of an existing via on the associated via layer, to form a DRC-clean PFVA relative to existing vias;
- and
- (2) removing any portion of a DRC-clean PFVA falling within the minimum via spacing rule of another DRC-clean PFVA.
An electronic circuit fabricated from a design layout representation thereof, the design layout comprising pure fill via areas (PFVA) for an associated via layer, said design layout being generated by the steps of:
- (1) removing any portion of a PFVA falling within a minimum via spacing rule of an existing via on the associated via layer, to form a DRC-clean PFVA relative to existing vias;
- and
- (2) removing any portion of a DRC-clean PFVA falling within the minimum via spacing rule of another DRC-clean PFVA.
A computer readable encoding of instructions for a computer, said instructions encoding a method for use with a design layout, said method for correcting spacing violations in pure fill via areas (PFVA) for an associated via layer of the design layout, said encoded method comprising the steps of:
- (1) removing any portion of a PFVA falling within a minimum via spacing rule of an existing via on the associated via layer, to form a DRC-clean PFVA relative to existing vias;
- and
- (2) removing any portion of a DRC-clean PFVA falling within the minimum via spacing rule of another DRC-clean PFVA.
An apparatus for processing one or more design files for an electronic circuit, the one or more design files encoding representations of a design layout of the electronic circuit, the design layout comprising pure fill via areas (PFVA) for an associated via layer, said apparatus comprising:
- first means for removing any portion of a PFVA falling within a minimum via spacing rule of an existing via on the associated via layer, to form a DRC-clean PFVA relative to existing vias;
- and
- second means for removing any portion of a DRC-clean PFVA falling within the minimum via spacing rule of another DRC-clean PFVA.
A method of making a computer readable media product that encodes a design file representation of a design layout of an electronic circuit, the design layout comprising pure fill via areas (PFVA) for an associated via layer, said method comprising the steps of:
- (1) removing any portion of a PFVA falling within a minimum via spacing rule of an existing via on the associated via layer, to form a DRC-clean PFVA relative to existing vias;
- and
- (2) removing any portion of a DRC-clean PFVA falling within the minimum via spacing rule of another DRC-clean PFVA.
Dependencies are inferred from the claim text.