Generalized fault model for defects and circuit marginalities
AssigneeIntel Corporation
InventorsSandip Kundu, Sanjay Sengupta, Dhiraj Goswami
Life of this patent
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Abstract
A generalized fault model. For one aspect, extracted faults may be modeled using a fault model in which at least one of the following is specified: multiple fault atoms, two or more impact conditions for a first set of excitation conditions, a relative priority of fault atoms within a set of fault atoms used to model the at least one extracted fault, a dynamic fault delay, and excitation conditions including at least a first mandatory excitation condition and at least a second optional excitation condition.
Claims24
A method comprising:
- receiving a list of extracted faults;
- and
- modeling at least one of the extracted faults by specifying at least one of the following:
- a) two or more impact conditions for a first set of excitation conditions,
- b) a dynamic fault delay, and
- c) excitation conditions including at least a first mandatory excitation condition and at least a second optional excitation condition.
A method comprising:
- modeling at least one fault in a faulty behavior list associated with an integrated circuit design by specifying at least one of:
- a) two or more fault atoms;
- b) two or more impact conditions for a first set of excitation conditions,
- c) a relative priority of fault atoms where more than one fault atom is included,
- d) a dynamic fault delay, and
- e) excitation conditions including at least a first mandatory
- excitation condition and at least a second optional excitation condition;
- and
- generating an associated test pattern in response to receiving the modeled fault.
A machine-readable storage medium storing data that, when executed by a machine, causes the machine to:
- model at least one of a plurality of extracted faults related to an integrated circuit design by specifying at least one of:
- a) two or more impact conditions for a first set of excitation conditions,
- b) a dynamic fault delay, and
- c) excitation conditions including at least a first mandatory excitation condition and at least a second optional excitation condition.
An apparatus comprising:
- a generalized fault modeler to output a model of at least one extracted fault associated with an integrated circuit design, the model to specify at least one of:
- a) two or more impact conditions for a first set of excitation conditions,
- b) a dynamic fault delay, and
- c) excitation conditions including at least a first mandatory excitation condition and at least a second optional excitation condition.
A method comprising:
- generating a first test pattern to satisfy a mandatory excitation condition specified in a fault model associated with a first extracted fault;
- and
- generating a second test pattern to satisfy an optional excitation condition specified in the fault model, the optional excitation condition to improve a quality of a test to identify the first extracted fault.
A system comprising:
- a bus;
- a processor coupled to the bus;
- and
- a memory, the memory to store data that, when executed by the processor, cause the system to:
- model at least a first extracted fault associated with an integrated circuit design by specifying at least one of:
- a) two or more impact conditions for a first set of excitation conditions,
- b) a dynamic fault delay, and
- c) excitation conditions including at least a first mandatory excitation condition and at least a second optional excitation condition.
Dependencies are inferred from the claim text.