System and method for selectively updating pointers used in conditionally executed load/store with update instructions

A system, comprising:

• a memory system and a processor coupled to the memory system;
• wherein the memory system comprises a conditional execution instruction and at least one target instruction, and wherein the conditional execution instruction specifies the at least one target instruction, a specified register of the processor, and a specified condition within the specified register, and wherein the conditional execution instruction comprises pointer update information;
• wherein the processor comprises:
• an instruction unit configured to fetch instructions from the memory system and to and decode the conditional execution instruction and the least one target instruction;
• an execution unit operably coupled to the instruction unit and configured to save a result of each of the at least one target instruction dependent upon the existence of the specified condition in the specified register during execution of the conditional execution instruction;
• and
• wherein in the event the at least one target instruction comprises an instruction involving a pointer subject to update, the execution unit is configured to update the pointer dependent upon the pointer update information.

A method for conditionally executing at least one instruction, the method comprising:

• inputting a conditional execution instruction and the at least one target instruction, wherein the conditional execution instruction specifies the at least one target instruction, a specified register, and a specified condition within the specified register, and wherein the conditional execution instruction comprises pointer update information;
• in the event the at least one target instruction comprises an instruction involving a pointer subject to update, updating the pointer dependent upon the pointer update information;
• and
• saving a result of each of the at least one target instruction dependent upon the specified condition within the specified register during execution of the conditional execution instruction.

A processor, comprising:

• means for inputting a conditional execution instruction and at least one target instruction, wherein the conditional execution instruction specifies the at least one target instruction, a specified register, and a specified condition within the specified register, and wherein the conditional execution instruction comprises pointer update information;
• means for, in the event the at least one target instruction comprises an instruction involving a pointer subject to update, updating the pointer dependent upon the pointer update information;
• and
• means for saving a result of each of the at least one target instruction dependent upon the specified condition within the specified register during execution of the conditional execution instruction.