Structure and method of cache memory data update

A structure of cache memory data updating applied to a cache system of a processor, comprising:

• an external memory to store received data temporarily and to be divided into several buffer blocks;
• a cache memory embedded in said local processor and mapped to said buffer blocks by addressing of a memory space;
• and
• a data loading mechanism that maps each said buffer block to said memory space in turn, wherein said processor addresses the addresses of said memory space in order so as to cause cache missing to load updated data from said buffer blocks.

A method of cache memory data updating applied to a cache system of a processor, comprising the steps of:

• dividing an external memory of said processor into several buffer blocks to store temporarily data received by the processor;
• addressing different addresses in a memory space to the same buffer block in said external memory;
• and
• when the processor is addressing said different addresses, cache missing in the cache system occurs so as to load into the same buffer block in said external memory according to the addressing of said addresses, thereby obtaining updated data of said buffer blocks in said cache system.

A method of cache memory data updating applied to the cache system of a processor, comprising the steps of:

• dividing an external memory into several buffer blocks to save temporarily data received by the processor;
• mapping said buffer blocks to certain memory space in turn;
• and
• when the processor is reading the memory space, cache missing in the cache system occurs so as to load the data in said buffer blocks in turn, thereby obtaining updated data of the buffer blocks.

A method of cache memory data updating applied to cache memory of a processor, comprising the steps of:

• dividing an external memory into several buffer blocks to save temporarily data received by the processor;
• mapping said buffer blocks in turn to a memory space with an address range and said cache memory capable of addressing the address range;
• and
• when the processor addressing said address range, cache missing occurring so that data in said buffer blocks is alternatively loaded to obtain updated data of the buffer blocks.