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US 2004/0064274 A1Published application
Residue calculating unit immune to power analysis
AssigneeRenesas Technology Corp.
InventorAtsuo Yamaguchi
Life of this patent
Estimating the term…
Abstract
A power-residue calculating unit includes a K register connected to a first internal bus for once storing an intermediate calculation result to be discarded when a power-residue calculation is executed in accordance with a binary method. Therefore even when data to be discarded appears during the calculation, a write into K register is performed, so that current in a write operation flows thereby improving immunity against Power Analysis.
Claims9
A power-residue calculating unit comprising:
- a first register group holding a first kind of data;
- a second register group holding a kind of data to be referred to concurrently with the data held in said first register group;
- a first internal bus connected to said first register group;
- a second internal bus connected to said second register group;
- a Montgomery multiplication residue calculation executing portion connected to said first and second internal buses for concurrently referring to values held in said first and second register groups and executing a Montgomery multiplication residue calculation;
- a power-residue calculation executing portion connected to said first and second internal buses and said Montgomery multiplication residue calculation executing portion for concurrently referring to values held in said first and second register groups, communicating data with said Montgomery multiplication residue calculation executing portion, and executing a power-residue calculation;
- and
- a pseudo calculation executing portion for executing in a pseudo manner an intermediate calculation process that can be omitted to obtain each calculation result of said Montgomery multiplication residue calculation and said power-residue calculation.
5 more elements
Dependencies are inferred from the claim text.