Method to avoid copper contamination of a via or dual damascene structure

A method for forming a conductive region in an integrated circuit device, comprising:

• providing a semiconductor substrate having semiconductor devices and conductive interconnects therein;
• forming a dielectric layer overlying the semiconductor substrate;
• forming an opening in the dielectric layer, wherein the opening overlies a conductive interconnect such that the bottom surface of the opening is formed by the conductive interconnect;
• forming a barrier layer on the bottom surface of the opening;
• removing at least a portion of the barrier layer such that barrier layer material is deposited on the sidewalls of the opening;
• cleaning the bottom surface of the opening;
• and
• forming the conductive region in the opening, such that the conductive region is in electrical contact with the underlying conductive interconnect.

A method for forming first and second conductive regions in an integrated circuit device, comprising:

• providing a semiconductor substrate having semiconductor devices and conductive interconnects therein;
• forming a first dielectric layer overlying the semiconductor substrate;
• forming a first opening in the first dielectric layer, wherein the first opening overlies a conductive interconnect such that the bottom surface of the first opening is formed by the underlying conductive surface;
• forming a second dielectric layer overlying the first dielectric layer;
• forming a second opening in the second dielectric layer, wherein a portion of the second opening overlies a portion of the first opening;
• forming a first barrier layer on the bottom surface of the first opening;
• removing at least a portion of the first barrier layer such that the first barrier layer material is deposited on the sidewalls of the first opening;
• cleaning the bottom surface of the first opening;
• and
• forming the first and the second conductive regions in the first and the second openings, respectively, such that the first conductive region is in electrical contact with the underlying conductive interconnect and such that the second conductive region is in electrical contact with the first conductive region.

A method for forming a conductive region in an integrated circuit device, comprising:

• providing a semiconductor substrate having semiconductor devices and conductive interconnects therein;
• forming in stacked relation overlying the semiconductor substrate, a first barrier layer, a first dielectric layer, a second barrier layer and a second dielectric layer;
• forming first and second openings-in the first and the second dielectric layers, respectively, wherein the first opening overlies a conductive interconnect, and wherein a portion of the second opening overlies a portion of the first opening;
• removing any remaining portions of the first and the second barrier layers from the bottom of the first and the second openings;
• forming a third barrier layer on the bottom surface of the first opening;
• removing at least a portion of the third barrier layer from the bottom surface to the sidewalls of the first opening;
• cleaning the bottom surface of the first opening;
• forming a fourth barrier layer on the bottom surface and the sidewalls of the first and the second openings;
• and
• forming the conductive region in the first and the second openings, respectively, such that the lower surface of the conductive region is in electrical contact with the underlying conductive interconnect.

A method for forming a conductive region in an integrated circuit device, comprising:

• providing a semiconductor substrate having semiconductor devices and conductive interconnects therein;
• forming in stacked relation overlying the semiconductor substrate, a first barrier layer, a first dielectric layer, a second barrier layer and a second dielectric layer;
• forming first and second openings in the first and the second dielectric layers, respectively, wherein the first opening overlies a conductive interconnect, and wherein a portion of the second opening overlies the first opening;
• forming a third barrier layer on the bottom surface of the first opening;
• removing at least a portion of the third barrier layer from the bottom surface to the sidewalls of the first opening;
• removing the first barrier layer from the bottom of the first openings;
• removing the second barrier layer from the bottom of the second openings;
• cleaning the bottom surface of the first opening;
• forming a fourth barrier layer on the bottom surface and the sidewalls of the first and the second openings;
• and
• forming the conductive region in the first and the second openings, respectively, such that the lower surface of the conductive region is in electrical contact with the underlying conductive interconnect.

A method for preventing contamination of a dielectric caused by diffusion of a contaminating material into the dielectric, wherein the dielectric has an opening therein, and wherein the contaminating material forms the bottom surface of the opening, said method comprising:

• (a) forming a barrier layer on the bottom surface of the opening overlying the contaminating material;
• (b) removing portions of the barrier layer from the bottom surface to the sidewalls of the opening;
• and
• (c) cleaning the bottom surface of the opening during which the contaminating material may be deposited on the sidewalls of the opening, wherein the contaminating material is prevented from diffusing into the dielectric material by the barrier layer material, and wherein the cleaning is performed in an environment containing a hydrogen species.

A method for forming a conductive region in an integrated circuit device, comprising:

• providing a semiconductor substrate having semiconductor devices and conductive interconnects therein;
• forming a dielectric layer overlying the semiconductor substrate;
• forming an opening in the dielectric layer, wherein the opening overlies a conductive interconnect such that the bottom surface of the opening is formed by the conductive interconnect;
• forming a barrier layer on the bottom surface of the opening;
• removing at least a portion of the barrier layer such that barrier layer material is deposited on the sidewalls of the opening;
• cleaning the bottom surface of the opening in an environment containing a hydrogen species;
• and
• forming the conductive region in the opening, such that the conductive region is in electrical contact with the underlying conductive interconnect.