Redundant via rule check in a multi-wide object class design layout

A method for testing via enclosure by geometries of a design layout, said vias connecting geometries of a first layer to geometries of a second layer, said method comprising the steps of:

• representing geometries on the first layer by a w0 set of objects;
• deriving w1 objects corresponding to the w0 objects;
• extending virtual edges of w1 objects outward by up to a predetermined amount to generate extended w1 objects as base class w1 objects;
• identifying w1 connection areas between the first layer and the second layer, each having at least one via located within a base class w1 object of the first layer;
• performing a w1 redundant via test on vias within each identified w1 connection area, said w1 redundant via test performed relative to the base class w1 objects;
• marking vias within any w1 connection area which fails the w1 redundant via test as a violation.

A method of making a computer readable media product that encodes a design file representation of a design layout of an electronic circuit, said design layout having vias connecting geometries of a first layer to geometries of a second layer, said method comprising the steps of:

• representing geometries on the first layer by a w0 set of objects;
• for i=1, n:
• deriving a wide class wi object set;
• identifying w1 connection areas between the first layer and the second layer, each having at least one via located within a w1 object of the first layer;
• performing a wi redundant via test on each identified wi connection area, said wi redundant via test performed relative to a base class w1 object set containing the identified wi connection area, said base class w1 formed by extending virtual edges of w1 objects inside of w0 objects;
• and
• identifying vias that fail the wi redundant via test;
• and
• correcting the identified failing vias.

A method of processing one or more design files for an electronic circuit, the one or more design files encoding representations of a design layout of the electronic circuit, said design layout having vias connecting geometries of a first layer to geometries of a second layer, said method comprising the steps of:

• representing geometries on the first layer by a w0 set of objects;
• for i=1, n:
• deriving a wide class wi object set;
• identifying wi connection areas between the first layer and the second layer, each having at least one via located within a wi object of the first layer;
• performing a wi redundant via test on each identified wi connection area, said wi redundant via test performed relative to a base class w1 object set containing the identified wi connection area, said base class w1 formed by extending virtual edges of w1 objects inside of w0 objects;
• and
• identifying vias that fail the wi redundant via test as violations.

An electronic circuit fabricated from a design layout representation thereof, said design layout having vias connecting geometries of a first layer to geometries of a second layer, said design layout being generated by the steps of:

• representing geometries on the first layer by a w0 set of objects;
• for i=1, n:
• deriving a wide class wi object set;
• identifying wi connection areas between the first layer and the second layer, each having at least one via located within a wi object of the first layer;
• performing a wi redundant via test on each identified w, connection area, said wi redundant via test performed relative to a base class w1 object set containing the identified wi connection area, said base class w1 formed by extending virtual edges of w1 objects inside of w0 objects;
• and
• identifying vias that fail the wi redundant via test;
• and
• correcting the identified failing vias.

A computer readable encoding of an electronic circuit design, the computer readable encoding comprising:

• one or more design file media encoding representations of vias connecting geometries of a first layer to geometries of a second layer;
• wherein the computer readable encoding of the electronic circuit design was generated by the steps of:
• representing geometries on the first layer by a w0 set of objects;
• for i=1, n:
• deriving a wide class wi object set;
• identifying wi connection areas between the first layer and the second layer, each having at least one via located within a wi object of the first layer;
• performing a wi redundant via test on each identified wi connection area, said wi redundant via test performed relative to a base class wi object set containing the identified wi connection area, said base class w1 formed by extending virtual edges of w1 objects inside of w0 objects;
• and
• identifying vias that fail the wi redundant via test;
• and
• correcting the identified failing vias.

An apparatus for processing one or more design files for an electronic circuit, the one or more design files encoding representations of a design layout of the electronic circuit, said design layout having vias connecting geometries of a first layer to geometries of a second layer, said apparatus comprising:

• means for deriving wide object classes w0, w1, . . . , wn corresponding to the first layer;
• means for identifying wi connection areas between the first layer and the second layer for each wide class wi object set, each having at least one via located within a wi object of the first layer;
• means for performing a wi redundant via test on each identified wi connection area, said wi redundant via test performed relative to a base class w1 object set containing the identified wi connection area, said base class w1 formed by extending virtual edges of w1 objects inside of w0 objects;
• and
• means for identifying vias that fail the wi redundant via test as violations.

A computer readable encoding of instructions for a computer, said instructions encoding a method for use with a design layout, for testing enclosure of vias by geometries of a design layout, said vias connecting geometries of a first layer to geometries of a second layer, said encoded method comprising the steps of:

• representing geometries on the first layer by a w0 set of objects;
• for i=1, n:
• deriving a wide class wi object set;
• identifying wi connection areas between the first layer and the second layer, each having at least one via located within a wi object of the first layer;
• performing a wi redundant via test on each identified wi connection area, said wi redundant via test performed relative to a base class w1 object set containing the identified wi connection area, said base class w1 formed by extending virtual edges of w1 objects inside of w0 objects;
• and
• marking vias that fail the wi redundant via test as a violation.