US 2004/0062102 A1 · Test system and method for testing memory circuits

Abstract

A first and a second memory circuit are tested in parallel. It is possible to activate the memory circuits depending on a circuit select signal, and it is possible to apply a control signal to the first and second memory circuits. The control signal initiates a function in the respective memory circuit depending on the activation of the first or second memory circuit. In testing the memory circuits, the circuit select signal is applied to the first memory circuit and the inverted circuit select signal is applied to the second memory circuit, so that the function is initiated in the first or in the second memory circuit depending on the circuit select signal.

Claims8

Dependent claims

A test system for testing a first memory circuit and a second memory circuit in parallel, the test system comprising:

a tester unit configured to generate a circuit select signal for activating the first and second memory circuits to receive signals in dependence on the circuit select signal;
the first memory circuit and the second memory circuit each having a test data generator circuit for generating test data for writing to memory cells of the respective memory circuit;
and
wherein the first memory circuit and the second memory circuit are connected to said tester unit in such a way as to simultaneously apply the circuit select signal to the first memory circuit in inverted form and to the second memory circuit in noninverted form.

1 more element

Dependencies are inferred from the claim text.

Test system and method for testing memory circuits

Life of this patent

Test system and method for testing memory circuits

Life of this patent

Abstract

Claims8