Flash memory structure and method of fabrication

A method for forming a flash memory structure on a semiconductor substrate, the method comprising:

• forming a plurality of parallel source lines with first conductivity type within the semiconductor substrate;
• forming two bit lines with first conductivity type on two sides of each source line and within the semiconductor substrate;
• forming a doped region with second conductivity type beneath and surrounding each bit line;
• forming a plurality of oxide-nitride-oxide (ONO) dielectric layers on the semiconductor substrate, and each ONO dielectric layer covering a channel of a corresponding bit line and each source line;
• forming a plurality of word lines on the semiconductor substrate and covering the ONO dielectric layers;
• and
• forming a contact plug in each bit line for electrically connecting to the bit line and a corresponding doped region beneath and surrounding the bit line.

A flash memory structure positioned on a semiconductor substrate, the flash memory structure comprising:

• a well formed in the semiconductor substrate with first conductivity type;
• a plurality of parallel word lines positioned on the said well;
• a plurality of parallel source lines with first conductivity type positioned within the said well;
• two bit lines with first conductivity type positioned on two sides of each source line and within the said well, the source lines and the bit lines being perpendicular to the word lines;
• a doped region with second conductivity type positioned beneath and surrounding each bit line;
• a contact plug positioned in each bit line for electrically connecting to the bit line and a corresponding doped region beneath and surrounding the bit line;
• and
• a oxide-nitride-oxide (ONO) dielectric layer positioned on an overlapped region of the said well and each word line.

A method for forming a flash memory structure on a semiconductor substrate, the method comprising:

• forming a well with first conductivity type, forming a plurality of parallel source lines with first conductivity type within the said well;
• forming two bit lines with first conductivity type on two sides of each source line and within the said well;
• forming a doped region with second conductivity type beneath and surrounding each bit line;
• forming a plurality of oxide-nitride-oxide (ONO) dielectric layers on the said well, and each ONO dielectric layer covering a channel of a corresponding bit line and each source line;
• forming a plurality of word lines on the said well and covering the ONO dielectric layers;
• and
• forming a contact plug in each bit line for electrically connecting to the bit line and a corresponding doped region beneath and surrounding the bit line.