US 2004/0061634 A1Published application

D/a converter with high jitter resistance

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsYasuo Morimoto, Toshio Kumamoto, Takashi Okuda

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Abstract

A D/A converter including a plurality of potential generating sections. They each receive a 1-bit signal from one of an input terminal and delay circuit, and a clock signal or inverted clock signal from an input section or inverter for inverting the clock signal. When the clock signal or inverted clock signal is at a first signal level, they generate a first reference potential or second reference potential in response to the signal level of the 1-bit signal. When the clock signal or inverted clock signal is at the second level, they generate an intermediate potential between the first and second reference potentials. The potentials generated by the plurality of potential generating sections are combined by a combining section. The D/A converter can improve resistance to jitter, and to simplify the configuration of a post-stage filter circuit.

Claims9

Dependent claims

A D/A converter comprising:

input means for inputting a 1-bit signal and a clock signal;
first delay means for delaying the 1-bit signal supplied from said input means;
inverting means for inverting the clock signal supplied from said input means;
first potential generating means for receiving the 1-bit signal and the clock signal supplied from said input means, for generating, when the clock signal is at a first level, one of a first reference potential and a second reference potential in response to the signal level of the 1-bit signal, and for generating, when the clock signal is at a second level, an intermediate potential between the first reference potential and the second reference potential;
second potential generating means for receiving the 1bit signal supplied from said input means and the clock signal inverted by said inverting means, for generating, when the inverted clock signal is at the first level, one of the first reference potential and the second reference potential in response to the signal level of the 1-bit signal, and for generating, when the inverted clock signal is at the second level, the intermediate potential between the first reference potential and the second reference potential;
third potential generating means for receiving the 1-bit signal delayed by said first delay means and the clock signal supplied from said input means, for generating, when the clock signal is at the first level, one of the first reference potential and the second reference potential in response to the signal level of the delayed 1-bit signal, and for generating, when the clock signal is at the second level, the intermediate potential between the first reference potential and the second reference potential;
fourth potential generating means for receiving the 1-bit signal delayed by said first delay means and the clock signal inverted by said inverting means, for generating, when the inverted clock signal is at the first level, one of the first reference potential and the second reference potential in response to the signal level of the delayed 1-bit signal, and for generating, when the inverted clock signal is at the second level, the intermediate potential between the first reference potential and the second reference potential;
and
combining means for combining the potentials output from said first to fourth potential generating means.

6 more elements

A D/A converter comprising:

input means for inputting a 1-bit signal and a clock signal with a data rate twice that of the 1-bit signal;
signal converting means for outputting, in synchronization with the clock signal supplied from said input means, a level signal assuming one of “1” and “−1” levels during a first half period of the 1-bit signal in response to the signal level of the 1-bit signal, and a level signal assuming a “0” level during a second half period of the 1-bit signal;
a plurality of delay means for delaying the level signal output from said signal converting means;
a plurality of potential generating means each for receiving the level signal output from one of said signal converting means and said plurality of delay means, and for generating one of a first reference potential, a second reference potential and an intermediate potential corresponding to the level signal;
and
combining means for combining the potentials generated by said a plurality of potential generating means.

3 more elements

Dependencies are inferred from the claim text.