Sram process monitor cell
AssigneeLSI Logic Corporation
InventorsCarl A. Monzel, Brandon R. Bartz
Life of this patent
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Abstract
A process monitor circuit useful for integrated circuit designs to provide manufacturing process tests for SRAM circuit structures incorporated in an integrated circuit design. In one aspect of the invention, the process monitor cell includes a plurality of SRAM circuit cells chained together in a manner to permit testing of a desired range of SRAM transistor power and a desired range of associated propagation delays. The process monitor cell thereby provides an accurate estimate of the quality of the fabrication process used to generate other functional SRAM cells within the integrated circuit design.
Claims18
A process monitor cell for use in testing an integrated circuit, said process monitor cell comprising:
- a counter for counting test events associated with SRAM devices of said integrated circuit;
- and
- an SRAM performance monitor circuit coupled to said counter for generating a test signal representing said test events.
A ring oscillator comprising:
- a plurality of SRAM columns including at least a first SRAM column and a last SRAM column wherein each SRAM column includes:
- an SRAM circuit including at least a storage element coupled to a logic high voltage source, a pass gate transistor having a gate input, an input signal path coupled to said gate input and an output bitline signal path coupled to another signal path of said pass gate transistor;
- a precharge transistor being of a type opposite that of said pass gate transistor and including a precharge gate input coupled to said input signal path and having one signal path coupled to a logic high voltage source and having another signal path coupled to said bitline signal path;
- and
- an inverter having an input coupled to said bitline signal path and having an output signal path,
- wherein the output signal path of the inverter of said each SRAM column is coupled to said input signal path of a next SRAM column of said plurality of SRAM columns and where the output signal path of the inverter of said last SRAM column is coupled to said input signal path of said first SRAM column.
An integrated circuit including:
- operational SRAM devices;
- and
- an SRAM process monitor cell for monitoring fabrication process quality impacts on said operational SRAM devices.
Dependencies are inferred from the claim text.