Quasi-synchronous multi-stage event synchronization apparatus

Abstract

The present invention relates to a quasi-synchronous multi-stage event synchronization apparatus by a phase lock loop (PLL) control circuit and a quasi-synchronous multi-stage synchronizer to tolerate clock uncertainty and speed up the synchronizing process between the asynchronous digital circuits from producing-end to consuming-end in the computer system. The phase lock loop (PLL) control circuit generates a pair of well-controlled clocks, PDU_CLK, CSM_CLK, assigned to producing-end and consuming-end and a pair of clock phase indicating signals, PDU_SYNC_PULSE, CSM_SYNC_PULSE, associated with the pair of well-controlled clocks. The quasi-synchronous multi-stage synchronizer routes the series of sync events into a synchronization stage with minimal synchronization delay from producing-end to consuming-end.

Dependencies are inferred from the claim text.