Data output circuit in combined SDR/DDR semiconductor memory device

A data output circuit in a combined SDR/DDR semiconductor memory device, the data output circuit comprising:

• a data output buffer that latches and outputs data output from a memory cell;
• and
• a first and a second data output drivers that generate output data in response to an output signal of the data output buffer,
• wherein the data output buffer comprises:
• an even data output buffer unit that latches and outputs even data, which will be output to a first data pin, in response to an even clock in a DDR mode, and that latches and outputs first data, which will be output to the first data pin, in response to a data output clock in an SDR mode;
• and
• an odd data output buffer unit that latches and outputs odd data, which will be output to the first data pin, in response to an odd clock in the DDR mode, and that latches and outputs second data, which will be output to a second data pin, in response to the data output clock.

A data output circuit in a combined SDR/DDR semiconductor memory device, the data output circuit comprising:

• a data output buffer that latches and outputs data output from a memory cell;
• and
• first and second data output drivers that drive first and second output pads to a predetermined voltage level in response to an output signal of the data output buffer,
• wherein the data output buffer includes a first data output buffer unit and a second data output buffer unit,
• wherein, in a DDR mode, the first and second data output buffer units are electrically connected to the first data output driver and latch even data and odd data that will be output to the first output pad in response to the rising edge and the falling edge of a clock signal, and
• wherein, in a SDR mode, the first data output buffer unit is electrically connected to the first data output driver and latches the data that will be output to the first output pad in response to the rising edge or the falling edge of the clock signal, and the second data output buffer unit is electrically connected to the second data output driver and latches the data that will be output to the second output pad in response to the rising edge or the falling edge of the clock signal.

A method of operating a data output circuit configured to run in a combined single data rate/double data rate (SDR/DDR) semiconductor device comprising:

• during a DRR mode, latching even data in response to an even clock using a first data latch and a third data latch;
• during the DRR mode, latching odd data in response to an odd clock using a second data latch and a fourth data latch;
• during a SDR mode, latching first data in response to a data output clock using the first data latch and the third data latch;
• during the SDR mode, latching second data in response to the data output clock using the second data latch and the fourth data latch;
• during the DDR mode, generating a first pull-up control signal and a first pull-down control signal using the first and third data latches, respectively, and also generating the first pull-up control signal and the first pull-down control signal using the second and fourth data latches, respectively;
• during the SDR mode, generating the first pull-up control signal and the first pull-down control signal using the first and the third data latches, respectively, and generating a second pull-up control signal and a second pull-down control signal using the second and the fourth data latches, respectively;
• driving a first output pad to a predetermined voltage level with a first data output driver in response to the first pull-up control signal and the first pull-down control signal;
• and
• driving a second output pad to a predetermined voltage level with a second data output driver in response to the second pull-up control signal and the second pull-down control signal.