US 2004/0057310 A1 · Non-volatile semiconductor memory

Abstract

A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has a first latch and a second latch that are selectively connected to the memory cell array and transfer data each other. A controller controls the reprogramming and retrieval circuits on data-reprogramming operation to and data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches in storing the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

Claims32

Dependent claims

A non-volatile semiconductor device comprising:

a memory cell array having electrically erasable programmable non-volatile memory cells;
a plurality of reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array, each reprogramming and retrieval circuit having a first latch and a second latch, the first latch being connected to a selected bit line of the memory cell array via a first transfer switch and a second transfer switch series-connected to each other, the second latch being connected to a connection node of the first and the second transfer switches via a third transfer switch, a data node of the second latch being connected to data input and output lines via column selection switches;
and
a controller that controls the reprogramming and retrieval circuits on data-reprogramming operation to and data-retrieval operation from the memory cell array.

1 more element

A non-volatile semiconductor device comprising:

a memory cell array having electrically erasable programmable non-volatile memory cells;
a plurality of reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array;
and
a controller that controls the reprogramming and retrieval circuits on data-reprogramming operation to and data-retrieval operation from the memory cell array,
wherein each reprogramming and retrieval circuit includes:
a first transistor provided between a sense node and a selected bit line of the memory cell array;
a second transistor having a gate connected to the sense node and a source to which a reference potential is applied, for detecting a potential level of the sense node;
a first latch connected to a drain of the second transistor via a third transistor that is selectively turned on;
a second latch connected to the drain of the second transistor via a fourth transistor that is selectively turned on and also connected to data input and output lines via a selection gate circuit;
a fifth transistor for selectively connecting the first latch to the selected bit line of the memory cell array and
a sixth transistor for selectively connecting the second latch to the sense node.

8 more elements

A non-volatile semiconductor device comprising:

a memory cell array having non-volatile memory cells, data being stored in a selected non-volatile memory cell in accordance with existence of a current flowing through the selected cell or a level of the current;
and
a sense amplifier circuit for retrieving the data on a selected bit line, the sense amplifier circuit including:
a sense node connected to the selected bit line via a clamp transistor;
a pre-charging circuit for pre-charging the bit line via the clamp transistor connected to the sense node;
an inverter having an input terminal connected to the sense node via transfer transistor;
and
a boosting capacitor, a first terminal thereof being connected to the sense node, the capacitor boosting a potential at the sense node using a second terminal as a drive terminal.

5 more elements

A non-volatile semiconductor device comprising:

a memory cell array having non-volatile memory cells, data being stored in a selected non-volatile memory cell in accordance with existence of a current flowing through the selected cell or a level of the current;
and
a sense amplifier circuit for retrieving the data on a selected bit line, the sense amplifier circuit including:
a sense node connected to the selected bit line via a clamp transistor;
a pre-charging circuit for pre-charging the bit line via the clamp transistor connected to the sense node;
a sense transistor, a source thereof being supplied with a reference potential;
a latch having a data node connected to a drain of the sense transistor via transfer transistor;
and
a boosting capacitor, one of two terminals thereof being connected to the sense node, the capacitor boosting a potential at the sense node using the other terminal as a drive terminal.

6 more elements

Dependencies are inferred from the claim text.

Non-volatile semiconductor memory

Life of this patent

Non-volatile semiconductor memory

Life of this patent

Abstract

Claims32