US 2004/0057307 A1 · Self-test circuit and a method for testing a memory with the self-test circuit

Abstract

A self-test circuit has an address generator unit for generating a test address for the purpose of testing a memory circuit and a control circuit that has signal inputs via which test commands can be applied and via which a memory access may be carried out. A first register is provided for storing an address difference value, in which case, as a result of a first test command, the address generator circuit increases the test address by the address difference value in the event of a subsequent memory access or, as a result of a second test command, the address generator circuit decreases the test address by the address difference value in the event of a subsequent memory access.

Claims12

Dependent claims

A self-test circuit, comprising:

an address generator circuit for generating a test address for testing a memory circuit;
a control circuit connected to said address generator circuit for controlling said address generator circuit, said control circuit having signal inputs for receiving test commands;
and
a register storing an address difference value and connected to said control circuit and to said address generator circuit, upon receiving a first test command said control circuit driving said address generator circuit to increase the test address by the address difference value in an event of a subsequent memory access, upon receiving a second test command said control circuit driving said address generator circuit to decrease the test address by the address difference value in an event of the subsequent memory access.

1 more element

Dependencies are inferred from the claim text.

Self-test circuit and a method for testing a memory with the self-test circuit

Life of this patent

Self-test circuit and a method for testing a memory with the self-test circuit

Life of this patent

Abstract

Claims12