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US 2004/0057290 A1Published application
Memory I/O buffer using shared read/write circuitry
AssigneeLSI Logic Corporation
InventorCarl A. Monzel
Life of this patent
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Abstract
A memory input-output (IO) buffer is provided, which includes a bit line, a data input-output line and a combined sense amplifier and write driver. The combined sense amplifier and write driver is coupled to the data input-output line and the first bit line and shares the same physical area on an integrated circuit.
Claims15
A memory input-output (IO) buffer comprising:
- a first bit line;
- a first data input-output line;
- and
- a combined sense amplifier and write driver coupled to the first data input-output line and the first bit line.
1 more element
A combined sense amplifier and write driver circuit comprising:
- first and second complementary bit lines;
- first and second complementary data input-output lines;
- and
- a selectively enabled latching amplifier coupled to the first and second complementary bit lines and the first and second complementary data input-output lines, wherein the latching amplifier is enabled during a read state and a write state and is disabled during an idle state.
1 more element
A memory input-output (IO) buffer comprising:
- first and second complementary bit lines;
- first and second complementary data input-output lines;
- a column multiplexer element coupled to the complementary bit lines;
- and
- combined read sense and write driver means, coupled between the column multiplexer element and the complementary data input-output lines, for sensing voltages on the complementary bit lines through the column multiplexer element during a read state and for driving voltages on the complementary bit lines through the column multiplexer element during a write state.
2 more elements
Dependencies are inferred from the claim text.