Self-aligned split-gate NAND flash memory and fabrication process

In a process of fabricating a NAND flash memory cell array, the steps of:

• forming an oxide layer on an active area in a silicon substrate, forming a first silicon layer on the oxide layer, forming a dielectric film on the first silicon layer, forming a second silicon layer on the dielectric film, etching away a portion of the second silicon layer to form a row of control gates with exposed side walls, forming an oxide on the side walls of the control gates, using the oxide on the side walls of the control gates as a mask, anisotropically etching away portions of the first silicon layer to form floating gates which are thereby self-aligned with and of greater lateral extent than the control gates, forming source diffusions in the active area of the substrate between the gates, forming a thermal oxide on the side edges of the floating gates and on other oxide surfaces, depositing a third silicon layer over the thermal oxide, removing portions of the third silicon layer to form a select gate next to the control gate at one end of the row and split gates between and self-aligned with the control gates, forming a bit line diffusion in the active area of the substrate near the select gate, and forming a bit line above the row and a bit line contact which interconnects the bit line and the bit line diffusion.

In a process of fabricating a NAND flash memory cell array, the steps of:

• forming an oxide layer on an active area in a silicon substrate, forming a first silicon layer on the oxide layer, forming a dielectric film on the first silicon layer, forming a second silicon layer on the dielectric film, etching away a portion of the second silicon layer to form a row of control gates with exposed side walls, forming an oxide on the side walls of the control gates, using the oxide on the side walls of the control gates as a mask, anisotropically etching away portions of the first silicon layer to form floating gates which are thereby self-aligned with and of greater lateral extent than the control gates, forming source diffusions in the active area of the substrate between the gates, forming a thermal oxide on the side edges of the floating gates and on other oxide surfaces, depositing a third silicon layer over the thermal oxide, removing portions of the third silicon layer to form select gates at opposite ends of the row and split gates between and self-aligned with the control gates, forming a bit line diffusion and a common source diffusion in the active area of the substrate near respective ones of the select gates, and forming a bit line above the row and a bit line contact which interconnects the bit line and the bit line diffusion.

A NAND flash memory cell array, comprising:

• a substrate having an active area, a plurality of vertically stacked pairs of floating gates and control gates arranged in rows above the active area, with the floating gates being relatively thin and having curved side edges and the control gates being positioned above the floating gates, erase gates interposed between and aligned with the stacked gates in each row, select gates adjacent to the stacked gates at opposite ends of each row, a bit line above each row, a bit line diffusion and a common source diffusion in the active area at opposite ends of each row near the select gates, a bit line contact interconnecting the bit line and the bit line diffusion in each row, relatively thin tunnel oxides between the curved side edges of the floating gates and adjacent ones of the erase and select gates, and source regions in the active area beneath the erase gates partially underlying the floating gates.

In a process of fabricating a NAND flash memory cell array, the steps of:

• forming an oxide layer on an active area in a silicon substrate, forming a first silicon layer on the oxide layer, forming a dielectric film on the first silicon layer, forming a second silicon layer on the dielectric film, etching away a portion of the second silicon layer to form a row of control gates with exposed side edges, forming an oxide on the side walls of the control gates, using the oxide on the side walls of the control gates as a mask, anisotropically etching away portions of the first silicon layer to form floating gates which are thereby self-aligned with and of greater lateral extent than the control gates, forming source diffusions in the active area of the substrate between the gates, forming a thermal oxide on the side edges of the floating gates and on other oxide surfaces, depositing a third silicon layer over the thermal oxide, removing portions of the third silicon layer to form select gates next to the control gates at opposite ends of the row and erase gates between and self-aligned with the control gates, forming a bit line diffusion and a common source diffusion in the active area at opposite ends of each row near the select gates, and forming a bit line above the row and a bit line contact which interconnects the bit line and the bit line diffusion.

A NAND flash memory cell array, comprising:

• a substrate having an active area, a plurality of vertically stacked pairs of floating gates and control gates arranged in rows above the active area, with the floating gates being relatively thin and having curved side edges and the control gates being positioned above the floating gates, row select gates adjacent to the stacked gates at opposite ends of each row, cell select gates interposed between and aligned with the stacked gates in each row, a bit line above each row, a bit line diffusion and a common source diffusion in the active area at opposite ends of each row near the row select gates, a bit line contact interconnecting the bit line and the bit line diffusion in each row, and relatively thin tunnel oxides between the curved side edges of the floating gates and adjacent ones of the select gates.

In a process of fabricating a NAND flash memory cell array, the steps of:

• forming an oxide layer on an active area in a silicon substrate, forming a first silicon layer on the oxide layer, forming a dielectric film on the first silicon layer, forming a second silicon layer on the dielectric film, etching away a portion of the second silicon layer to form a row of control gates with exposed side walls, forming an oxide on the side walls of the control gates, using the oxide on the side walls of the control gates as a mask, anisotropically etching away portions of the first silicon layer to form floating gates which are thereby self-aligned with and of greater lateral extent than the control gates, forming a thermal oxide on the side edges of the floating gates and on other oxide surfaces, depositing a third silicon layer over the thermal oxide, removing portions of the third silicon layer to form row select gates next to the control gates at opposite ends of the row and cell select gates between and self-aligned with the control gates, forming a bit line diffusion and a common source diffusion in the active area at opposite ends of each row near the row select gates, and forming a bit line above the row and a bit line contact which interconnects the bit line and the bit line diffusion.

A NAND flash memory cell array, comprising:

• a substrate having an active area, a plurality of vertically stacked pairs of floating gates and control gates arranged in rows above the active area, with the floating gates being relatively thin and having curved side edges and the control gates being positioned above the floating gates, row select gates adjacent to the stacked gates at opposite ends of each row, shallow trenches formed in the active area of the substrate between the stacked gates, cell select gates extending into the trenches and aligned with the stacked gates in each row, a bit line above each row, a bit line diffusion and a common source diffusion in the active area at opposite ends of each row near the row select gates, a bit line contact interconnecting the bit line and the bit line diffusion in each row, relatively thin tunnel oxides between the curved side edges of the floating gates and adjacent ones of the select gates, and source regions in the active area beneath the cell select gates.

In a NAND flash memory cell array:

• a silicon substrate having an active area, an oxide layer formed on the substrate above the active area, a plurality of relatively thin floating gates having the side edges with a rounded curvature above the oxide layer, a plurality of control gates positioned above and in vertical alignment with the floating gates, the control gages being substantially thicker in vertical dimension and narrower in horizontal dimension than the underlying floating gates, row select gates adjacent to and self-aligned with the control gates at opposite ends of a row of gates, cell select gates interposed between the control gates, relatively thin tunnel oxides between the rounded side edges of the floating gates and the select gates, relatively thick dielectric between the select gates and the control gates, a thin dielectric between each of the floating gates and the silicon substrate, a relatively thick dielectric between the row select gate and the silicon substrate, a bit line diffusion region and a common source diffusion region partially underlying the select gates at opposite ends of the row, a bit line, and a bit line contact interconnecting the bit line and the bit line diffusion.