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US 2004/0057259 A1Published application
Negative charge pump with bulk biasing
AssigneeAtmel Corporation, a Delaware Corporation
InventorsGiorgio Oddone, Massimiliano Frulio, Luca Figini, Fabio Tassan Caser
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Abstract
An n-channel MOS transistor negative-voltage charge pump is disclosed in which the bulks of the n-channel MOS transistors are biased in such a manner as to prevent turning on the parasitic bipolar transistor inherent in the CMOS environment of the charge pump structure.
Claims4
A negative-voltage charge pump having a plurality of operating phases and comprising a plurality of stages, each stage comprising at least two n-channel MOS transistors each including bulk regions, each of said stages also including a parasitic bipolar transistor, said bulk regions switchably coupled during each of said operating phases to a circuit node having a potential such that said parasitic bipolar transistor will not turn on.
A negative charge-pump stage comprising:
- an input node;
- an output node;
- a phase-A clock signal node;
- a phase-D clock signal node;
- a first n-channel MOS transistor having a drain coupled to said input node, a source coupled to said output node, a gate, and a bulk region coupled to a bulk-region node;
- a second n-channel MOS transistor having a drain, a source coupled to said output node, a gate coupled to said input node, and a bulk region coupled to a bulk-region node;
- a first capacitor coupled between said input node and said phase-A clock signal node;
- a second capacitor coupled between said drain of said second n-channel MOS transistor and said phase-D clock signal node;
- a first n-channel MOS bulk-switch transistor having a drain coupled to said bulk-region node, a source coupled to said input node, a gate coupled to said drain of said second n-channel MOS transistor, and a bulk region coupled to said bulk-region node;
- and
- a second n-channel MOS bulk-switch transistor having a drain coupled to said bulk-region node, a source coupled to said output node, a gate coupled to said input node, and a bulk region coupled to said bulk-region node.
8 more elements
A negative-voltage charge pump comprising:
- a phase-A clock signal node;
- a phase-B clock signal node;
- a phase-C clock signal node;
- a phase-D clock signal node;
- a first charge-pump stage including:
- a first-stage input node coupled to a fixed potential;
- a first-stage output node;
- a first n-channel MOS transistor having a drain coupled to said first-stage input node, a source coupled to said first-stage output node, a gate, and a bulk region coupled to a first-stage bulk-region node;
- a second n-channel MOS transistor having a drain, a source coupled to said first-stage output node, a gate coupled to said first-stage input node, and a bulk region coupled to said first-stage bulk-region node;
- a first capacitor coupled between said first-stage input node and said phase-A clock signal node;
- a second capacitor coupled between said drain of said second n-channel MOS transistor and said phase-D clock signal node;
- a first n-channel MOS bulk-switch transistor having a drain coupled to said bulk-region node, a source coupled to said first-stage input node, a gate coupled to said drain of said second n-channel MOS transistor, and a bulk region coupled to said first-stage bulk-region node;
- a second n-channel MOS bulk-switch transistor having a drain coupled to said first-stage bulk-region node, a source coupled to said first-stage output node, a gate coupled to said first-stage input node, and a bulk region coupled to said first-stage bulk-region node;
- a second charge-pump stage including:
- a second-stage input node coupled to said first-stage output node;
- a second-stage output node;
- a third n-channel MOS transistor having a drain coupled to said second-stage input node, a source coupled to said second-stage output node, a gate, and a bulk region coupled to a second-stage bulk-region node;
- a fourth n-channel MOS transistor having a drain, a source coupled to said second-stage output node, a gate coupled to said second-stage input node, and a bulk region coupled to said second-stage bulk-region node;
- a third capacitor coupled between said second-stage input node and said phase-C clock signal node;
- a fourth capacitor coupled between said drain of said fourth n-channel MOS transistor and said phase-B clock signal node;
- a third n-channel MOS bulk-switch transistor having a drain coupled to said second-stage bulk-region node, a source coupled to said second-stage input node, a gate coupled to said drain of said fourth n-channel MOS transistor, and a bulk region coupled to said second-stage bulk-region node;
- a fourth n-channel MOS bulk-switch transistor having a drain coupled to said second-stage bulk-region node, a source coupled to said second-stage output node, a gate coupled to said second-stage input node, and a bulk region coupled to said second-stage bulk-region node;
- a third charge-pump stage including:
- a third-stage input node coupled to said second-stage output node;
- a third-stage output node;
- a fifth n-channel MOS transistor having a drain coupled to said third-stage input node, a source coupled to said third-stage output node, a gate, and a bulk region coupled to a third-stage bulk-region node;
- a sixth n-channel MOS transistor having a drain, a source coupled to said third-stage output node, a gate coupled to said third-stage input node, and a bulk region coupled to said third-stage bulk-region node;
- a fifth capacitor coupled between said third-stage input node and said phase-A clock signal node;
- a sixth capacitor coupled between said drain of said sixth n-channel MOS transistor and said phase-D clock signal node;
- a seventh capacitor coupled between said third-stage output node and said phase-C clock signal node;
- a fifth n-channel MOS bulk-switch transistor having a drain coupled to said third-stage bulk-region node, a source coupled to said third-stage input node, a gate coupled to said drain of said sixth n-channel MOS transistor, and a bulk region coupled to said third-stage bulk-region node;
- a sixth n-channel MOS bulk-switch transistor having a drain coupled to said third-stage bulk-region node, a source coupled to said third-stage output node, a gate coupled to said third-stage input node, and a bulk region coupled to said third-stage bulk-region node;
- and
- an output stage including a seventh n-channel MOS transistor having source coupled to said charge-pump output node, a drain coupled to said second-stage output node, a gate coupled to said drain of said sixth n-channel MOS transistor, and a bulk region coupled to said second-stage bulk-region node.
31 more elements
Dependencies are inferred from the claim text.