Semiconductor device

A semiconductor device having a first circuit area on a main surface of a semiconductor chip and a plurality of wiring layers which are formed on said main surface of said semiconductor chip,

• said wiring layers including a first wiring layer which is comprised of copper as main element, with a plurality of first lines being formed thereof, and a second wiring layer which is a upmost wiring layer among said wiring layers and comprised of aluminum as main element, with a plurality of second lines being formed thereof,
• said second lines of said second wiring layer being made lower in sheet resistance than said first lines of said first wiring layer which is immediately below said second wiring layer,
• said second lines of said second wiring layer having a plurality of external terminals, a plurality of first power lines which are laid to run around an outer edge of said first circuit area, and a plurality of second power lines which are laid to connect directly said external terminals to said first power lines respectively.

A semiconductor device having a first circuit area on a main surface of a semiconductor chip and a plurality of wiring layers which are formed on said main surface of said semiconductor chip,

• said wiring layers including a first wiring layer which is comprised of copper as main element, with a plurality of first lines being formed thereof, and a second wiring layer which is a upmost wiring layer among said wiring layers and comprised of aluminum as main element, with a plurality of second lines being formed thereof,
• said second lines of said second wiring layer being made larger in thickness than said first lines of said first wiring layer which is immediately below said second wiring layer,
• said second lines of said-second wiring layer having a plurality of external terminals, a plurality of first power lines which are laid to run around an outer edge of said first circuit area, a plurality of second power lines which are laid to connect directly said external terminals to said first power lines respectively, and a plurality of third power lines which are laid in said first circuit area and connected directly to said innermost first power line among said first power lines.

A semiconductor device having a first circuit area on a main surface of a semiconductor chip and a plurality of wiring layers which are formed on said main surface of said semiconductor chip,

• said wiring layers including a first wiring layer which is comprised of copper as main element, with a plurality of first lines being formed thereof, and a second wiring layer which is a upmost wiring layer among said wiring layers and comprised of aluminum as main element, with a plurality of second lines being formed thereof,
• said second lines of said second wiring layer being made lower in sheet resistance than said first lines of said first wiring layer which is immediately below said second wiring layer,
• said second lines of said second wiring layer having a plurality of external terminals, a plurality of first power lines which are laid to run around an outer edge of said first circuit area, a plurality of second power lines which are laid to connect directly said external terminals to said first power lines respectively, and a plurality of third power lines which are laid in said first circuit area and connected directly to the innermost first power line among said first power lines.

A semiconductor device having a first circuit area on a main surface of a semiconductor chip and a plurality of wiring layers which are formed on said main surface of said semiconductor chip,

• said wiring layers including a first wiring layer, with a plurality of first lines being formed thereof, and a second wiring layer which is a upmost wiring layer among said wiring layers, with a plurality of second lines which are lower in sheet resistance than said first wiring layers being formed thereof,
• said second lines of said second wiring layer having a plurality of external terminals, a plurality of first power lines which are laid to run around an outer edge of said first circuit area, and a plurality of second power lines which are laid to connect directly said external terminals to said first power lines respectively.

A semiconductor device having a plurality of wiring layers formed on a semiconductor chip, a upmost wiring layer, which is comprised of aluminum as main element and includes first lines, being made lower in sheet resistance than said wiring layer which is immediately below the upmost wiring layer, is comprised of copper as main element, and includes second lines.

A semiconductor device having a plurality of external terminals which are formed of a wiring layer with a lowest sheet resistance among a plurality of wiring layers formed on a semiconductor chip, and a plurality of power lines which are laid to run around an outer edge of a first circuit area of said semiconductor chip, said external terminals being connected directly to said power lines respectively through said wiring layer with said lowest sheet resistance.

A semiconductor device having a plurality of wiring layers formed on a semiconductor chip, a upmost wiring layer being lowest in sheet resistance among all wiring layers and having a layout of only external terminals and power lines.