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US 2004/0056313 A1Published application
Apparatus and circuit having reduced leakage current and method therefor
AssigneeIntel Corporation
InventorMark E. Schuelein
Life of this patent
Estimating the term…
Abstract
Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage generator that selectively increases the voltage potential on the channel region of a transistor relative to the source region of the transistor. The voltage potential may be provided to a diffusion region in the well regions with transistors.
Claims21
An apparatus comprising;
- a semiconductor substrate having a first well region and a second well region in which at least a portion of p-channel metal oxide semiconductor (PMOS) transistors are formed;
- a first diffusion region in the first well region;
- a second diffusion region in the second well region;
- a first transistor to couple the first diffusion region to a first power supply voltage potential when the PMOS transistors are in a disabled operational mode;
- and
- a second transistor to couple the second diffusion region to the first power supply voltage potential when the PMOS transistors are in a disabled operational mode.
3 more elements
A system comprising:
- a flash memory array;
- and
- a processor coupled to the flash memory array, the processor comprising:
- a semiconductor substrate having a first well region and a second well region in which at least a portion of p-channel metal oxide semiconductor (PMOS) transistors are formed, the first well region including a first diffusion region and the second well region including a second diffusion region;
- a first transistor to couple the first diffusion region to a first power supply voltage potential when the PMOS transistors are in a disabled operational mode;
- a second transistor to couple the second diffusion region to the first power supply voltage potential when the PMOS transistors are in the disabled operational mode.
3 more elements
A method of putting at least a portion of an integrated circuit into standby mode comprising:
- providing a first power supply voltage potential to a plurality of well regions in a semiconductor substrate by enabling a plurality of transistors, each of the plurality of well regions being coupled to at least one of the plurality of transistors.
Dependencies are inferred from the claim text.