Power semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorsWataru Saito, Ichiro Omura, Kozo Kinoshita
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Abstract
A power semiconductor device is disclosed, which comprises a semiconductor layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, which are periodically formed in the lateral direction, and a power semiconductor element including the semiconductor layers that are formed periodically, wherein a distribution of an amount of an impurity in a vertical direction of the first semiconductor layer differs from a distribution of an amount of an impurity in the vertical direction of the second semiconductor layer.
Claims15
A power semiconductor device comprising:
- a semiconductor layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, which are periodically formed in the lateral direction;
- and
- a power semiconductor element including the semiconductor layers that are formed periodically;
- wherein a distribution of an amount of an impurity in a vertical direction of the first semiconductor layer differs from a distribution of an amount of an impurity in the vertical direction of the second semiconductor layer.
A power semiconductor device comprising:
- a first semiconductor layer of a first conductivity type;
- a first main electrode electrically connected to the first semiconductor layer;
- second semiconductor layers of a second conductivity type formed within the first semiconductor layer and periodically arranged in a lateral direction, a distribution of an amount of an impurity in a vertical direction of the second semiconductor layers being differ from a distribution of an amount of the impurity in the vertical direction of the first semiconductor layer;
- a third semiconductor layer of the second conductivity type selectively formed in surfaces of the first semiconductor layer and the second semiconductor layer;
- a fourth semiconductor layer of the first conductivity type selectively formed in a surface of the third semiconductor layer;
- a second main electrode formed to be connected to the surface of the third semiconductor layer and a surface of the fourth semiconductor layer;
- and
- a control electrode formed on the first semiconductor layer, the third semiconductor layer and the fourth semiconductor layer with a gate insulating film interposed therebetween.
Dependencies are inferred from the claim text.