Memory architecture with memory cell groups
AssigneesInfineon Technologies AG, Kabushiki Kaisha Toshiba
InventorsMichael Jacob, Andreas Hilliger, Thomas Roehr, Susumo Shuto, Toru Ozaki
Life of this patent
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Abstract
An improved cell design for series memory architecture is disclosed. The improved cell design facilitates the formation of capacitors using a single etch process instead of two, as conventionally required. In one embodiment, each capacitor of a capacitor pair is provided with at least one plug contacting a common diffusion region of two adjacent cell transistors. In another embodiment, a large plug with sufficient overlap to the bottom electrodes of pair of capacitors is used.
Claims14
An integrated circuit comprising:
- at least one memory cell pair having first and second memory cells arranged in a memory group, a memory cell includes a cell transistor having first and second diffusion regions and a cell capacitor having a dielectric layer between first and second electrodes, wherein the cell transistors of the memory cell pair share a common second diffusion region;
- a first bottom electrode plug coupling the first electrode of the first memory cell capacitor to the common second diffusion region;
- a second bottom electrode plug coupling the first electrode of the second memory cell capacitor to the common second diffusion region;
- and
- the second electrode of the first memory cell capacitor is coupled to the first diffusion region of the first memory cell transistor and the second electrode of the second memory cell capacitor is coupled to the first diffusion region of the second cell transistor.
An integrated circuit comprising:
- at least one memory cell pair having first and second memory cells arranged in a memory group, a memory cell includes a cell transistor having first and second diffusion regions and a cell capacitor having a dielectric layer between first and second electrodes, wherein the cell transistors of the memory cell pair share a common second diffusion region;
- a bottom electrode plug coupling the first electrodes of the capacitors of the memory cell pair to the common second diffusion region, the bottom electrode plug sufficiently large to provide sufficient overlap to the first electrodes;
- and
- the second electrodes of the capacitors coupled to first diffusion regions of respective cell transistors.
Dependencies are inferred from the claim text.