Etchant for wires, a method for manufacturing the wires using the etchant, a thin film transistor array substrate and a method for manufacturing the same including the method

A method of manufacturing a thin film transistor array panel comprising:

• forming a gate wire including a gate line and a gate electrode;
• forming a gate insulating layer covering the gate wire;
• forming a semiconductor layer on the gate insulating layer of the gate electrode;
• and
• forming a data wire including a source electrode, a drain electrode and a data line on the semiconductor layer or the gate insulating layer,
• wherein, the gate wire or the data wire is formed with a first conductive film made of Mo or Mo alloy, wherein the first conductive film is patterned using HNO3 of 0.1 to 10%, H3PO4 of 65 to 55%, CH3COOH of 5 to 20%, stabilizer of 0.1 to 5% and the other ultra pure water, wherein the stabilizer is represented as a formula M(OH)x.Ly, wherein in the formula, the M is Zn, Sn, Cr, Al, Ba, Fe, Ti, Si or B, the L is H2O, NH3, CN, COR(herein, R is an alkyl having the number of carbon of 1 to 5), or NNR(herein, R is an alkyl having the number of carbon of 1 to 5), whrein x is 2 or 3, and y is 0, 1, 2, or 3.

A thin film transistor array panel, comprising:

• a gate wire formed on an insulating substrate and including a gate line and a gate pad connected to the gate line;
• a gate insulating layer covering the gate wire;
• a semiconductor layer formed on the gate insulating layer;
• a data wire formed on the gate insulating layer or the semiconductor layer and including a data line, a source electrode connected to the data line and formed on the semiconductor layer and a drain electrode formed on semiconductor layer disposed opposite the source electrode in relation to the gate electrode;
• a passivation layer covering the data wire;
• and
• a conductor pattern made of IZO and formed in the passivation layer,
• wherein, the gate wire or the data wire comprises a first conductive film made of Mo or Mo alloy.