US 2004/0025075 A1 · System and method for compensating for supply voltage induced clock delay mismatches

Abstract

Various systems and methods providing signal delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog implementation a buffer with an adjustable delay may be used to minimize the delay mismatch between clock trees. The delay of the adjustable-delay buffer is controlled by bias voltages that determine the charging and discharging current to the adjustable buffer. A phase detector circuit is used to compare the clock phases for rising and falling edges, and to adjust the bias voltages that control these edges. In a digital implementation a selector switch, responsive to a phase detector, may be used to route clock signals through circuit elements to delay clock signals.

Claims29

Dependent claims

A system for compensating for phase differences between a plurality of signals associated with a plurality of signal levels, comprising:

at least one phase comparator for comparing a phase of a first signal associated with a first signal level with a phase of a second signal associated with a second signal level, and for generating at least one compensation signal indicative of a phase difference between the first signal and the second signal;
and
at least one delay adjuster coupled to the at least one phase comparator and responsive to the at least one compensation signal, for delaying the first signal to compensate for the phase difference between the first signal and the second signal.

A system for compensating for phase differences between a plurality of signals, comprising:

a level adjuster for modifying a signal level of a signal to generate a first signal associated with a first signal level that is different than a second signal level associated with a second signal;
at least one phase comparator for comparing a phase of the first signal with a phase of the second signal, and for generating at least one compensation signal indicative of a phase difference between the first signal and the second signal;
and
at least one delay adjuster coupled to the at least one phase comparator and responsive to the at least one compensation signal, for delaying at least one of the first signal and the second signal to compensate for the phase difference between the first signal and the second signal.

1 more element

A circuit for compensating for phase differences between a plurality of signals associated with a plurality of signal levels, comprising:

a rising edge phase comparator for comparing a rising edge of a first signal associated with a first signal level with a rising edge of a second signal associated with a second signal level, for generating a rising edge compensation signal indicative of a phase difference between the rising edge of the first signal and the rising edge of the second signal;
a falling edge phase comparator for comparing a falling edge of the first signal with a falling edge of the second signal, for generating a falling edge compensation signal indicative of a phase difference between the falling edge of the first signal and the falling edge of the second signal;
and
an adjustable delay buffer coupled to the rising edge comparator and the falling edge comparator, for delaying the rising edge of the first signal in response to the rising edge compensation signal and for delaying the falling edge of the first signal in response to the falling edge compensation signal.

1 more element

Dependencies are inferred from the claim text.

System and method for compensating for supply voltage induced clock delay mismatches

Life of this patent

System and method for compensating for supply voltage induced clock delay mismatches

Life of this patent

Abstract

Claims29