US 2004/0024997 A1 · Test with immediate and skip processor instruction

Abstract

A processor is disclosed herein that may execute an instruction that includes an immediate value and a reference to a register accessible to the processor. The instruction causes the processor to perform a test using the immediate value and the contents of the register referenced in the instruction. Based on the outcome of test, the subsequent instruction is executed or skipped. Further, the instruction includes at least one bit that specifies how the test is to be performed. The bit may specify that the immediate value is to be compared to the register value, or that the immediate value is used to mask the register value and the masked register value has one or more of its bits tested.

Claims20

Dependent claims

A processor executing a plurality of instructions, comprising:

an arithmetic logic unit;
and
a plurality of registers coupled to the ALU, each register programmable to store a register value;
wherein said processor executes a test and skip instruction that includes an immediate value and a reference to a register, performs a comparison using the immediate value and the register value stored in the referenced register, and causes the processor to execute or not execute a subsequent instruction that follows the test and skip instruction based on the comparison.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

10/632,214Filed 31 Jul 2003

Priority

EP 03291910.230 Jul 2003

Published

5 Feb 2004

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

G06F 9/30134
Organisation of register space, e.g. banked or distributed register file: register stacks; shift registers
G06F 9/30072
Arrangements for executing specific machine instructions: to perform conditional operations, e.g. using predicates or guards
G06F 9/30167
Decoding the operand specifier, e.g. specifier format: of immediate specifier, e.g. constants
G06F 9/30181
Arrangements for executing machine instructions, e.g. instruction decode: instruction operation extension or modification

Test with immediate and skip processor instruction

Life of this patent

Test with immediate and skip processor instruction

Life of this patent

Abstract

Claims20