Retry mechanism for blocking interfaces

A HyperTransport-to-PCI (Peripheral Component Interconnect) bridge comprising:

• a PCI target interface unit connected to a first signal line for receiving requests from at least one PCI source unit, said requests requiring responses to be sent back to the respective PCI source unit, said requests being placed by the respective PCI source unit by asserting a request signal on said first signal line, said request signal being deasserted by the respective PCI source unit when a response is sent back to the respective PCI source unit;
• and
• a HyperTransport source interface unit connected to send signals corresponding to said received requests to a HyperTransport compliant target device;
• wherein said PCI target interface unit is further connected to a second signal line to send a retry request to the current PCI source unit for requesting the current PCI source unit to deassert its request signal although a response has not yet been sent back, and to reassert the request signal later, and
• wherein said PCI target interface unit is further connected to a third signal line to send to the current PCI source unit a ready signal together with said retry request, said ready signal indicating whether the request received from the current PCI source unit could be processed by said HyperTransport source interface unit.

A southbridge device for bridging a low-speed data channel to a high-speed data channel in a computer system, said southbridge device comprising:

• a low-speed interface unit connected to a first signal line for receiving requests from at least one requestor, said requests requiring responses to be sent back to the respective requester, said requests being placed by the respective requestor by asserting a request signal on said first signal line, said request signal being deasserted by the respective requester when a response is sent back to the respective requestor;
• and
• a high-speed interface unit connected to send signals corresponding to said received requests to an upstream target device;
• wherein said low-speed interface unit is further connected to a second signal line to send a retry request to the current requestor for requesting the current requestor to deassert its request signal although a response has not yet been sent back, and to reassert the request signal later, and
• wherein said low-speed interface unit is further connected to a third signal line to send to the current requestor a ready signal together with said retry request, said ready signal indicating whether the request received from the current requestor could be processed by said high-speed interface unit.

A method of operating an integrated circuit chip, the method comprising:

• receiving requests from at least one requestor, said requests requiring responses to be sent back to the respective requester, said requests being placed by the respective requestor by asserting a request signal, said request signal being deasserted by the respective requestor when a response is sent back to the respective requestor;
• and
• processing the received requests;
• wherein method further comprises:
• sending a retry request to the current requestor for requesting the current requestor to deassert its request signal although a response has not yet been sent back, and to reassert the request signal later;
• and
• sending a ready signal to the current requestor together with said retry request, said ready signal indicating whether the request received from the current requestor could already be processed.

A method of operating a PCI (Peripheral Component Interconnect) device, the method comprising:

• sending a request to a PCI target device by asserting a request signal, said request requiring a response;
• receiving a retry request and a ready signal from said PCI target device, said ready signal indicating whether the request sent to said PCI target device could be processed by said PCI target device;
• determining whether to deassert said request signal although a response has not yet been received, and if so, deasserting the request signal and reasserting it later;
• and
• deasserting said request signal when the response is received,
• wherein reasserting the request signal comprises determining whether to send a modified request if the ready signal indicated that the request sent to said PCI target device could not be processed by said PCI target device.

A computer system comprising:

• a PCI (Peripheral Component Interconnect) device;
• and
• a southbridge connected to said PCI device,
• wherein said PCI device is capable of sending a request to said southbridge by asserting a request signal, said southbridge is capable of sending a response back to said PCI device, and said PCI device is arranged to deassert said request signal when receiving said response,
• wherein said southbridge is further arranged to send a retry request to said PCI device for requesting said PCI device to deassert its request signal although a response has not yet been sent back, and to reassert the request signal later,
• wherein said southbridge is further arranged to send a ready signal to said PCI device together with said retry request, said ready signal indicating whether the request received from the current requester could be processed.