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AssigneeFujitsu Limited
InventorKiyoshi Inoue
Estimating the term…
A circuit verification apparatus, a circuit verification program and a circuit verification method are provided in which in the verification of a circuit according to software, the probability that an accumulation circuit such as a queue circuit, etc., changes into a saturated state can be increased without changing the logic of the circuit to be verified, thus making it possible to shorten the time required for the circuit verification. The circuit verification apparatus, which verifies an operation of the circuit to be verified when a queue circuit description operation part (45) is saturated, a verified circuit description part (40) for performing the operation of the circuit to be verified, a test control part (31) for generating an operation control signal to control an operation speed of the verified circuit description part (40), a delay processing part (34) for controlling the operation control signal to change the queue circuit description operation part (45) into a saturated state, and a confirmation signal monitoring part (33) for monitoring a confirmation signal representing that the queue circuit description operation part (45) has been changed into the saturated state in an operation of the verified circuit description section (40).
A circuit verification apparatus which verifies an operation of a circuit when an accumulation circuit included in the circuit to be verified becomes a saturated state, said apparatus comprising:
A circuit verification program stored in a computer readable medium which makes a computer verify an operation of a circuit when an accumulation circuit included in the circuit to be verified becomes a saturated state,
A circuit verification method which verifies an operation of a circuit when an accumulation circuit included in the circuit to be verified becomes a saturated state,
Dependencies are inferred from the claim text.