On chip network with memory device address decoding

An integrated circuit (IC), comprising:

• an on chip network (OCN) for transferring packets between a plurality of ports;
• a plurality of processing elements, each including a bus and a memory device coupled to the bus that is programmed with port addresses, wherein a transaction on a bus indicating another port is decoded into a corresponding port address by the memory device;
• and
• a plurality of bus gaskets, each coupled to a corresponding bus and to a corresponding one of the plurality of ports, each including a processor interface that generates packets and a port interface, coupled to the processor interface, that sends and receives the packets between the ports and that uses the decoded address as a destination port address.

A method of providing communication between a plurality of processing elements integrated on a chip, comprising:

• providing an on chip network (OCN) that transfers packets between a plurality of ports, wherein each port is associated with a corresponding one of the processing elements and conforms to a consistent port interface protocol;
• programming a memory device associated with each processing element with addresses of each of the plurality of ports;
• generating packets including one or more datums for transfer via the OCN;
• each memory device providing a port address in response to detecting a processing element transaction indicating a different port;
• and
• submitting a transfer request of a packet to the OCN including a port address provided from the memory device.