Method and apparatus to facilitate detecting a slow node in a circuit layout

A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for detecting one or more slow nodes in an integrated circuit layout, the method comprising:

• receiving the integrated circuit layout;
• inserting repeaters into signal lines of the integrated circuit layout to define a set of nets;
• producing an R/C model for each net;
• obtaining a timing model for each driver and receiver in the integrated circuit layout, wherein the timing model specifies a non-linear circuit model for each driver and a non-linear circuit model for each receiver;
• performing a circuit simulation using the timing model for each driver and receiver and the R/C model for each net;
• and
• using a result of the circuit simulation to identify one or more slow nodes in the integrated circuit layout.

An apparatus for detecting one or more slow nodes in an integrated circuit layout, comprising:

• a receiving mechanism that is configured to receive the integrated circuit layout;
• an inserting mechanism that is configured to insert repeaters into signal lines of the integrated circuit layout to define a set of nets;
• a model producing mechanism that is configured to produce an R/C model for each net;
• a timing model obtaining mechanism that is configured to obtain a timing model for each driver and receiver in the integrated circuit layout, wherein the timing model specifies a non-linear circuit model for each driver and a non-linear circuit model for each receiver;
• a simulation performing mechanism that is configured to perform a circuit simulation using the timing model for each driver and receiver and the R/C model for each net;
• and
• an identifying mechanism that is configured to identify one or more slow nodes in the integrated circuit layout using a result of the circuit simulation.