Method for fabricating a buried bit line for a semiconductor memory
AssigneeInfineon Technologies AG
InventorsVeronika Polei, Mayk Rohrich
Life of this patent
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Abstract
In a method for fabricating a buried bit line for a semiconductor memory, the buried bit line is produced as a diffusion region using a dopant source including polysilicon that has previously been applied above the region intended for the buried bit line. This keeps the extent of diffusion within limits and means that the doped polysilicon is particularly suitable for the formation of the insulating oxide region above the buried bit line, due to the rapid oxidation.
Claims7
A method for fabricating a buried bit line for a semiconductor memory, which comprises:
- producing strip-like doped regions parallel to and at distances from one another in a semiconductor body, the regions being adapted to act as bit lines and as source/drain regions of a respective memory transistor;
- applying laterally with respect to the doped regions, in each case, one layer sequence adapted to act as a gate dielectric and including a lower boundary layer, a storage layer, and an upper boundary layer;
- forming an oxide region in each case on a side of the doped regions remote from the semiconductor body, the oxide region being thicker than the lower boundary layer;
- before the upper boundary layer is applied, applying a sacrificial layer made from polysilicon and a material selectively etchable with respect to a material of the storage layer to the storage layer;
- producing openings in the sacrificial layer, the storage layer, and the lower boundary layer, extending to the semiconductor body, by using a mask;
- introducing doped polysilicon into the openings;
- removing the sacrificial layer;
- and
- producing the upper boundary layer on the storage layer and oxidizing at least a proportion of the polysilicon to form the oxide region.
A method for fabricating a buried bit line for a semiconductor memory, which comprises:
- producing strip-like doped regions parallel to and at distances from one another in a semiconductor body, the strip-like doped regions being adapted to act as bit lines and as source/drain regions of a respective memory transistor;
- applying laterally with respect to the doped regions, in each case, one layer sequence adapted to act as a gate dielectric and including a lower boundary layer, a storage layer, and an upper boundary layer;
- and
- forming an oxide region thicker than the lower boundary layer, in each case, on a side of the doped region remote from the semiconductor body;
- before producing the upper boundary layer, applying a sacrificial layer with a topside to the storage layer;
- producing openings with lateral walls in the sacrificial layer, the storage layer, and the lower boundary layer, by using a mask;
- introducing dopant into implantation regions of the semiconductor body through the openings;
- etching back the lateral walls of the openings and a topside of the sacrificial layer at an etching rate sufficient to form smooth sides on the sacrificial layer, the storage layer, and the lower boundary layer;
- removing residues of the sacrificial layer selectively with respect to the storage layer;
- and
- producing the upper boundary layer on the storage layer and forming an oxide region on a free surface of the semiconductor body, in each case between the sides.
Dependencies are inferred from the claim text.