US 2004/0017878 A1Published application

Shift-register circuit

AssigneeAu Optronics Corporation

InventorWein-Town Sun

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Abstract

A shift-register circuit. The input circuit receives the input pulse and outputs a high-voltage level input signal when the input pulse is at high voltage level. The level shifting circuit includes a first PMOS transistor having a first gate, a first drain and a first source coupled to a first voltage VDD, a second PMOS transistor having a second gate coupled to the first drain, a second drain coupled to the first gate and a second source coupled to the first voltage VDD, a first inverse logic gate coupled to the first drain and having an output terminal, a second inverse logic gate coupled to the second drain and having an inverse output terminal coupled to the input circuit, a first NMOS transistor having a third gate coupled to the input circuit, a third drain coupled to the first drain and a third source coupled to a second voltage VSS, a second NMOS transistor having a fourth gate coupled to the second gate and a fourth drain coupled to the second drain and a fourth source coupled to the second voltage VSS. The output circuit is coupled to the output terminal for outputting the shift-register signal.

Claims14

Dependent claims

A shift-register circuit for a first clock signal, a second clock signal and an input pulse to output a shift-register signal, comprising:

an input circuit for receiving the input pulse and outputting a high-voltage level input signal when the input pulse is at high voltage level;
a level shifting circuit is coupled to the input circuit, comprising:
a first PMOS transistor having a first gate, a first drain and a first source coupled to a first voltage VDD;
a second PMOS transistor having a second gate coupled to the first drain, a second drain coupled to the first gate and a second source coupled to the first voltage VDD;
a first NMOS transistor having a third gate coupled to the first gate, a third drain coupled to the first drain and a third source coupled to an inverse input terminal;
a second NMOS transistor having a fourth gate coupled to the second gate, a fourth drain coupled to the second drain and a fourth source coupled to an input terminal;
a third NMOS transistor having a fifth gate coupled to the fourth source, a fifth drain coupled to the first source and a output terminal and a fifth source coupled to a second voltage VSS;
a fourth NMOS transistor having a sixth gate coupled to the third source, a sixth drain coupled to the second drain and the input circuit and a sixth source coupled to the second voltage VSS;
a fifth NMOS transistor having a seventh gate coupled to the input circuit, a seventh drain coupled to the third source and a seventh source coupled to the second voltage VSS;
a sixth NMOS transistor having an eighth gate coupled to the input circuit, an eighth drain coupled to the fourth source and an eighth source coupled to the second voltage VSS;
and
an output circuit is coupled to the output terminal for outputting the shift-register signal.

9 more elements

A shift-register circuit for a first clock signal, a second clock signal and an input pulse to output a shift-register signal, comprising:

an input circuit for receiving the input pulse and outputting a high-voltage level input signal when the input pulse is at high voltage level;
a level shifting circuit is coupled to the input circuit, comprising:
a first PMOS transistor having a first gate, a first drain and a first source coupled to a first voltage VDD;
a second PMOS transistor having a second gate coupled to the first drain, a second drain coupled to the first gate and a second source coupled to the first voltage VDD;
a first inverse logic gate coupled to the first drain and having an output terminal;
a second inverse logic gate coupled to the second drain and having an inverse output terminal coupled to the input circuit;
a first NMOS transistor having a third gate coupled to the input circuit, a third drain coupled to the first drain and a third source coupled to a second voltage VSS;
a second NMOS transistor having a fourth gate coupled to the second gate, a fourth drain coupled to the second drain and a fourth source coupled to the second voltage VSS;
and
an output circuit is coupled to the output terminal for outputting the shift-register signal.

7 more elements

A shift-register circuit for a first clock signal, a second clock signal and an input pulse to output a shift-register signal, comprising:

an input circuit for receiving the input pulse and outputting a high-voltage level input signal when the input pulse is at high voltage level;
a level shifting circuit is coupled to the input circuit, comprising:
a first PMOS transistor having a first gate, a first drain and a first source coupled to a first voltage VDD;
a second PMOS transistor having a second gate coupled to the first drain, a second drain coupled to the first gate and a second source coupled to the first voltage VDD;
a first inverse logic gate coupled to the first drain and having an output terminal;
a second inverse logic gate coupled to the second drain and having an inverse output terminal;
a first NMOS transistor having a third gate coupled to the first voltage VDD, a third drain coupled to the first drain and a third source;
a second NMOS transistor having a fourth gate coupled to the first voltage VDD, a fourth source and a fourth drain coupled to the second drain;
a third NMOS transistor having a fifth gate, a fifth drain coupled to the third source and a fifth source coupled to the second voltage VSS;
a fourth NMOS transistor having a sixth gate, a sixth drain coupled to the third source and a sixth source coupled to the second voltage VSS;
and
an output circuit is coupled to the output terminal for outputting the shift-register signal.

9 more elements

A shift-register circuit for a first clock signal, a second clock signal and an input pulse to output a shift-register signal, comprising:

an input circuit for receiving the input pulse and outputting a high-voltage level input signal when the input pulse is at high voltage level;
a level shifting circuit is coupled to the input circuit, comprising:
a first PMOS transistor having a first gate, a first drain and a first source coupled to a first voltage VDD;
a second PMOS transistor having a second gate coupled to the first drain, a second drain coupled to the first gate and a second source coupled to the first voltage VDD;
a first inverse logic gate coupled to the first drain and having an output terminal;
a second inverse logic gate coupled to the second drain and having an inverse output terminal;
a first NMOS transistor having a third gate coupled to the first voltage VDD, a third drain coupled to the first drain and a third source;
a second NMOS transistor having a fourth gate coupled to the first voltage VDD, a fourth source and a fourth drain coupled to the second drain;
a third NMOS transistor having a fifth gate coupled to the input circuit, a fifth drain coupled to the first gate and the fourth source and a fifth source coupled to the second voltage VSS;
a fourth NMOS transistor having a sixth gate coupled to the input circuit, a sixth drain coupled to the third source and the second gate and a sixth source coupled to the second voltage VSS;
and
an output circuit is coupled to the output terminal for outputting the shift-register signal.

9 more elements

Dependencies are inferred from the claim text.