US 2004/0017671 A1 · Reducing electro magnetic interference (EMI) in integrated circuits operating on both analog and digital signals

Abstract

EMI caused on a sensitive pin by large electric current flowing through a load pin when driving a high load is reduced or substantially eliminated. An equal amount of current, but in opposite direction, is caused to be flown in another pin (“third pin”) located close to the load pin. As a result, the EMI caused by the third pin cancels the EMI generated by the load pin. During a discharge phase, a fourth pin carries and equal amount of current, but in opposite direction, to that in the load pin. The third and fourth pins may be formed by power supply pin and ground pin. A control path may avoid a path from the third pin to the fourth pin during both the charging and discharging phases. In addition, the high load may be driven by a programmable driver which uses an amount of current proportionate to the extent of load, thereby avoiding parasitic currents. EMI is further reduced as a result.

Claims37

Dependent claims

A method of reducing electro magnetic interference (EMI) caused by a first pin on a second pin, said first pin and said second pin being contained in a package of an integrated circuit, said first pin carrying a strong signal, and said second pin carrying a weaker signal, said method comprising:

providing a third pin;
causing said third pin to carry a second signal, wherein said second signal is equal in magnitude to said strong signal, but has a direction opposite to that of said strong signal,
whereby an EMI introduced by said first pin on said second pin is substantially canceled by an EMI introduced by said third pin.

A reduction circuit for reducing electro magnetic interference (EMI) caused by a first pin on a second pin, said first pin and said second pin being contained in a package of an integrated circuit, said first pin carrying a strong signal, and second pin carrying a weaker signal, said reduction circuit comprising:

a third pin;
and
an output drive logic coupled to said third pin and said first pin, said output drive logic causing said third pin to carry a second signal, wherein said second signal is equal in magnitude to said strong signal, but has a direction opposite to that of said strong signal,
whereby an EMI introduced by said first pin on said second pin is substantially canceled by an EMI introduced by said third pin.

1 more element

A device comprising:

a processing unit;
a package coupled to said processing unit, said package containing a first pin and a second pin, said first pin carrying a strong signal, and said second pin carrying a weaker signal;
and
a reduction circuit for reducing electro magnetic interference (EMI) caused by said first pin on said second pin, said reduction circuit comprising:
a third pin;
and
an output drive logic coupled to said third pin and said first pin, said output drive logic causing said third pin to carry a second signal, wherein said second signal is equal in magnitude to said strong signal, but has a direction opposite to that of said strong signal,
whereby an EMI introduced by said first pin on said second pin is substantially canceled by an EMI introduced by said third pin.

5 more elements

Dependencies are inferred from the claim text.

Reducing electro magnetic interference (EMI) in integrated circuits operating on both analog and digital signals

Life of this patent

Reducing electro magnetic interference (EMI) in integrated circuits operating on both analog and digital signals

Life of this patent

Abstract

Claims37