US 2004/0017243 A1Published application

Multi-phase clock generation circuit

AssigneeNEC Corporation

InventorTsutomu Sasaki

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Abstract

A multi-phase clock generation circuit includes a clock generation circuit, first frequency divider circuit, first clock selection circuit, second to nth frequency divider circuits, second to nth clock selection circuits, and clock selection control section. The clock generation circuit generates 2n (n is a positive integer) reference clock signals having the same frequency and different phases. The frequency divider circuit frequency-divides one of the reference clock signals by 2 to generate clock signals 180° out of phase with each other. The first clock selection circuit selects one of each of the clock signals and a corresponding reference clock signal and outputs the selected signals as clock pulses. Each of the second to nth frequency divider circuits frequency-divides a clock pulse to generate clock signals 180° out of phase with each other. Each of the second to nth clock selection circuits selects one of each of the clock signals and a corresponding one of the reference clock signals to output the selected signals as clock pulses. The clock selection control section controls the first to nth clock selection circuits in accordance with a set frequency division ratio.

Claims12

Dependent claims

A multi-phase clock generation circuit comprising:

reference clock signal generation means for generating 2n (n is a positive integer) reference clock signals having the same frequency, the plurality of reference clock signals having different phases;
first frequency division means for frequency-dividing one of the plurality of reference clock signals from said reference clock signal generation means by 2 to generate first and second clock signals 180° out of phase with each other on the basis of frequency division outputs;
first clock selection means for selecting one of each of the first and second clock signals from said first frequency division means and a corresponding reference clock signal and outputting the selected signals as first and second clock pulses;
second to nth frequency division means each of which frequency-divides a clock pulse from said first clock selection means to generate (2m−1)th to (2m+1−2)th (m is a positive integer of not less than 2) clock signals 180° out of phase with each other on the basis of frequency division outputs;
second to nth clock selection means each of which selects one of each of the clock signals from said second to nth frequency division means and a corresponding one of the reference clock signals to output the selected signals as (2m−1)th to (2m+1−2)th clock pulses;
and
clock selection control means for controlling said first to nth clock selection means in accordance with a set frequency division ratio.

4 more elements

Dependencies are inferred from the claim text.